PIC16F87 Datasheet, PDF (17/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Details
on
page
Bank 1
80h⁽²⁾ INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 ^{26, 135}
81h
82h⁽²⁾
83h⁽²⁾
84h⁽²⁾
85h
OPTION
PCL
STATUS
FSR
TRISA
RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
Indirect Data Memory Address Pointer
TRISA7 TRISA6 TRISA5⁽³⁾ PORTA Data Direction Register (TRISA<4:0>)
PS0
1111 1111 18, 69
0000 0000 135
C
0001 1xxx 17
xxxx xxxx 135
1111 1111 52, 126
86h
TRISB
PORTB Data Direction Register
1111 1111 58, 85
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
8Ah^(1,2)
8Bh⁽²⁾
—
PCLATH
INTCON
Unimplemented
—
—
GIE
PEIE
—
Write Buffer for the upper 5 bits of the Program Counter
TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
—
---0 0000
0000 000x
—
135
19, 69,
77
8Ch
PIE1
8Dh
PIE2
—
OSFIE
ADIE
CMIE
RCIE
—
TXIE
EEIE
SSPIE
—
CCP1IE
—
TMR2IE
—
TMR1IE -000 0000 ^{20, 80}
—
00-0 ---- 22, 34
8Eh
PCON
—
—
—
—
—
—
POR
BOR ---- --qq 24
8Fh
OSCCON
—
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0 -000 0000 40
90h
OSCTUNE
—
—
91h
—
Unimplemented
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0 --00 0000 38
—
—
92h
PR2
Timer2 Period Register
93h
SSPADD Synchronous Serial Port (I²C mode) Address Register
1111 1111 80, 85
0000 0000 95
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 88, 95
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 97, 99
99h
SPBRG
Baud Rate Generator Register
0000 0000 99, 103
9Ah
—
Unimplemented
9Bh
ANSEL⁽⁴⁾
—
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
—
120
ANS0 -111 1111 ¹²⁰
9Ch
CMCON
C2OUT C1OUT C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111 121,
126, 128
9Dh
CVRCON CVREN CVROE CVRR
—
CVR3
9Eh
ADRESL⁽⁴⁾ A/D Result Register Low Byte
9Fh
ADCON1⁽⁴⁾ ADFM ADCS2
VCFG1
VCFG0
—
CVR2
—
CVR1
—
CVR0
—
000- 0000 126, 128
xxxx xxxx ¹²⁰
0000 ---- ^{52, 115,}
120
Legend:
Note 1:
2:
3:
4:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
PIC16F88 device only.
 2003 Microchip Technology Inc.
Preliminary
DS30487B-page 15