PIC16F87 Datasheet, PDF (109/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
FIGURE 11-7:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
START
RB2/SDO/RX/DT pin bit bit 0 bit 1
START
bit 8 STOP bit bit 0
bit
bit 8 STOP
bit
Load RSR
Read
Bit 8 = 0, Data Byte
Bit 8 = 1, Address Byte
Word 1
RCREG
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN = 1.
FIGURE 11-8:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
START
RB2/SDO/RX/DT pin bit bit 0 bit 1
START
bit 8 STOP bit bit 0
bit
bit 8 STOP
bit
Load RSR
Read
Bit 8 = 1, Address Byte
Bit 8 = 0, Data Byte
Word 1
RCREG
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN was not updated and still = 0.
TABLE 11-9: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
0Bh, 8Bh, INTCON GIE
10Bh,18Bh
PEIE TMR0IE INTE RBIE TMR0IF INTF
R0IF 0000 000x 0000 000u
0Ch
PIR1
—
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
18h
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah
RCREG USART Receive Register
0000 0000 0000 0000
8Ch
PIE1
—
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
98h
TXSTA CSRC TX9 TXEN SYNC —
BRGH TRMT TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
 2003 Microchip Technology Inc.
Preliminary
DS30487B-page 107