PIC16F87 Datasheet, PDF (34/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
3.7 Writing to FLASH Program
Memory
FLASH program memory may only be written to if the
destination address is in a segment of memory that is
not write protected, as defined in bits WRT1:WRT0 of
the device configuration word (Register 15-1). FLASH
program memory must be written in four-word blocks.
A block consists of four words with sequential
addresses, with a lower boundary defined by an
address, where EEADR<1:0> = 00. At the same time,
all block writes to program memory are done as write
only operations. The program memory must first be
erased. The write operation is edge-aligned, and
cannot occur across boundaries.
To write to the program memory, the data must first be
loaded into the buffer registers. There are four 14-bit
buffer registers and they are addressed by the low
2 bits of EEADR.
Loading data into the buffer registers is accomplished
via the EEADR, EEADT, EECON1 and EECON2
registers as follows:
• Set EECON1 PGD and WREN
• Write address to EEADRH:EEADR
• Write data to EEDATA:EEDATH
• Write 55, AA to EECON2
• Set WR bit in EECON1
There are 4 buffer register words and all four locations
MUST be written to with correct data.
After the “BSF EECON1,WR” instruction, if
EEADR ≠ xxxxxx11, then a short write will occur.
This short write only transfers the data to the buffer reg-
ister. The WR bit will be cleared in hardware after 1
cycle. The core will not halt and there will be no
EEWHLT signal generated.
After the “BSF EECON1,WR” instruction, if
EEADR = xxxxxx11, then a long write will occur. This
will simultaneously transfer the data from
EEDATH:EEDATA to the buffer registers and begin the
write of all four words. The processor will execute the
next instruction and then ignore the subsequent
instruction. The user should place NOP instructions into
the second words. The processor will then halt internal
operations for typically 2 msec in which the write takes
place. This is not SLEEP mode, as the clocks and
peripherals will continue to run. After the write cycle,
the processor will resume operation with the 3rd
instruction after the EECON1 write instruction.
After each long write, the 4 buffer registers will be reset
to 3FFF.
FIGURE 3-1:
BLOCK WRITES TO FLASH PROGRAM MEMORY
75
07
0
EEDATH
EEDATA
6
8
First word of block
to be written
All buffers are
transferred
to FLASH
automatically
after this word
is written
14
EEADR<1:0>
= 00
Buffer Register
14
EEADR<1:0>
= 01
Buffer Register
14
14
EEADR<1:0>
= 10
Buffer Register
EEADR<1:0>
= 11
Buffer Register
Program Memory
DS30487B-page 32
Preliminary
 2003 Microchip Technology Inc.