PIC16F87 Datasheet, PDF (44/214 Pages) Microchip Technology – 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology

PIC16F87/88
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF<2:0> ≠ 000)
1. IRCF bits are modified to a different INTOSC/
INTOSC postscaler frequency.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. The IOFS bit is set.
5. Oscillator switchover is complete.
4.6.6
OSCILLATOR DELAY UPON
POWER-UP, WAKE-UP AND
CLOCK SWITCHING
Table 4-3 shows the different delays invoked for vari-
ous clock switching sequences. It also shows the
delays invoked for POR and wake-up.
TABLE 4-3: OSCILLATOR DELAY EXAMPLES
Switch From Switch To
Frequency
Oscillator Delay
Comments
SLEEP/POR
INTRC
T1OSC
INTOSC/
INTOSC
Postscaler
INTRC/SLEEP EC, RC
31.25 kHz
32.768 kHz
125 kHz - 8 MHz
DC - 20 MHz
5 µs - 10 µs (approx.)
CPU Start-up⁽¹⁾
Following a wake-up from SLEEP mode or
POR, CPU start-up is invoked to allow the
CPU to become ready for code execution.
INTRC
EC, RC
(31.25 kHz)
DC - 20 MHz
SLEEP
LP, XT, HS 32.768 kHz - 20 MHz 1024 Clock Cycles Following a change from INTRC, an OST
(OST)
of 1024 cycles must occur.
INTRC
INTOSC/
(31.25 kHz) INTOSC
Postscaler
125 kHz - 8 MHz
4 ms
Refer to Section 4.6.4 “Modifying the
IRCF bits” for further details.
Note 1: The 5 µs-10 µs start-up delay is based on a 1 MHz system clock.
DS30487B-page 42
Preliminary
 2003 Microchip Technology Inc.