PIC17C44 Datasheet, PDF (90/241 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
FIGURE 13-5: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
BRG output
(shift clock)
TX
(RA5/TX/CK pin)
TXIF bit
Word 1
Start Bit
Bit 0
Bit 1
Word 1
TRMT bit
Word 1
Transmit Shift Reg
Bit 7/8 _{Stop Bit}
FIGURE 13-6: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
BRG output
(shift clock)
TX
(RA5/TX/CK pin)
TXIF bit
Word 1
Word 2
Start Bit
Bit 0
Bit 1
Word 1
Bit 7/8 Stop Bit
Start Bit
Word 2
Bit 0
TRMT bit
Word 1
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
Word 2
Transmit Shift Reg.
TABLE 13-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address
Name
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
16h, Bank 1 PIR
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TXIF
RCIF 0000 0010 0000 0010
13h, Bank 0 RCSTA
SPEN
RX9 SREN CREN
—
FERR OERR
RX9D 0000 -00x 0000 -00u
16h, Bank 0 TXREG Serial port transmit register
xxxx xxxx uuuu uuuu
17h, Bank 1 PIE
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TXIE
RCIE 0000 0000 0000 0000
15h, Bank 0 TXSTA
CSRC
TX9 TXEN SYNC
—
—
TRMT
TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG Baud rate generator register
xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous
transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 90
© 1996 Microchip Technology Inc.