PIC17C44 Datasheet, PDF (33/241 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

FIGURE 6-5: PIC17C42 REGISTER FILE
MAP
Addr Unbanked
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
INDF0
FSR0
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
Bank 0
Bank 1 ⁽¹⁾
Bank 2 ⁽¹⁾
Bank 3 ⁽¹⁾
10h PORTA
DDRC
TMR1
PW1DCL
11h
DDRB
PORTC
TMR2
PW2DCL
12h PORTB
DDRD
TMR3L PW1DCH
13h
RCSTA
PORTD
TMR3H PW2DCH
14h RCREG
DDRE
PR1
CA2L
15h
TXSTA
PORTE
PR2
CA2H
16h TXREG
PIR
PR3L/CA1L TCON1
17h SPBRG
PIE
PR3H/CA1H TCON2
18h
1Fh
20h
General
Purpose
RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. All
other SFRs ignore the Bank Select Register
(BSR) bits.
PIC17C4X
FIGURE 6-6: PIC17CR42/42A/43/R43/44
REGISTER FILE MAP
Addr Unbanked
00h
INDF0
01h
FSR0
02h
PCL
03h PCLATH
04h ALUSTA
05h
T0STA
06h CPUSTA
07h INTSTA
08h
INDF1
09h
FSR1
0Ah WREG
0Bh TMR0L
0Ch TMR0H
0Dh TBLPTRL
0Eh TBLPTRH
0Fh
BSR
Bank 0 Bank 1 ⁽¹⁾ Bank 2 ⁽¹⁾ Bank 3 ⁽¹⁾
10h
PORTA
11h
DDRB
12h PORTB
13h
RCSTA
14h RCREG
15h
TXSTA
16h TXREG
17h SPBRG
18h PRODL
19h PRODH
1Ah
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
PIR
PIE
TMR1
TMR2
TMR3L
TMR3H
PR1
PR2
PR3L/CA1L
PR3H/CA1H
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
CA2H
TCON1
TCON2
1Fh
20h
General
Purpose
RAM ⁽²⁾
General
Purpose
RAM ⁽²⁾
FFh
Note 1: SFR file locations 10h - 17h are banked. All
other SFRs ignore the Bank Select Register
(BSR) bits.
2: General Purpose Registers (GPR) locations
20h - FFh and 120h - 1FFh are banked. All
other GPRs ignore the Bank Select Register
(BSR) bits.
© 1996 Microchip Technology Inc.
DS30412C-page 33