PIC17C44 Datasheet, PDF (105/241 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
14.4 Power-down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP instruction. This clears the Watchdog Timer and
postscaler (if enabled). The PD bit is cleared and the
TO bit is set (in the CPUSTA register). In SLEEP mode,
the oscillator driver is turned off. The I/O ports maintain
their status (driving high, low, or hi-impedance).
The MCLR/VPP pin must be at a logic high level
(VIHMC). A WDT time-out RESET does not drive the
MCLR/VPP pin low.
14.4.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
• A POR reset
• External reset input on MCLR/VPP pin
• WDT Reset (if WDT was enabled)
• Interrupt from RA0/INT pin, RB port change,
T0CKI interrupt, or some Peripheral Interrupts
The following peripheral interrupts can wake-up from
SLEEP:
• Capture1 interrupt
• Capture2 interrupt
• USART synchronous slave transmit interrupt
• USART synchronous slave receive interrupt
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
Any reset event will cause a device reset. Any interrupt
event is considered a continuation of program execu-
tion. The TO and PD bits in the CPUSTA register can
be used to determine the cause of device reset. The
PD bit, which is set on power-up, is cleared when
SLEEP is invoked. The TO bit is cleared if WDT
time-out occurred (and caused wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GLINTD bit. If the GLINTD
bit is set (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the
GLINTD bit is clear (enabled), the device executes the
instruction after the SLEEP instruction and then
branches to the interrupt vector address. In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOP after the
SLEEP instruction.
Note:
If the global interrupts are disabled
(GLINTD is set), but any interrupt source
has both its interrupt enable bit and the cor-
responding interrupt flag bits set, the
device will immediately wake-up from
sleep. The TO bit is set, and the PD bit is
cleared.
The WDT is cleared when the device wake from
SLEEP, regardless of the source of wake-up.
14.4.1.1 WAKE-UP DELAY
When the oscillator type is configured in XT or LF
mode, the Oscillator Start-up Timer (OST) is activated
on wake-up. The OST will keep the device in reset for
1024TOSC. This needs to be taken into account when
considering the interrupt response time when coming
out of SLEEP.
FIGURE 14-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC1
CLKOUT(4)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Tost(2)
INT
(RA0/INT pin)
INTF flag
Interrupt Latency (2)
GLINTD bit
INSTRUCTION FLOW
Processor
in SLEEP
PC
PC
PC+1
PC+2
0004h
0005h
Instruction
fetched
Instruction
executed
Inst (PC) = SLEEP
Inst (PC-1)
Inst (PC+1)
SLEEP
Inst (PC+2)
Inst (PC+1)
Dummy Cycle
Note 1: XT or LF oscillator mode assumed.
2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode.
3: When GLINTD = 0 processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
© 1996 Microchip Technology Inc.
DS30412C-page 105