PIC17C44 Datasheet, PDF (131/241 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Forced NOP
Return from Interrupt
[ label ] RETFIE
None
TOS → (PC);
0 → GLINTD;
PCLATH is unchanged.
GLINTD
0000 0000 0000 0101
Return from Interrupt. Stack is POP’ed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by clearing
the GLINTD bit. GLINTD is the global
interrupt disable bit (CPUSTA<4>).
1
2
Q2
Read
register
T0STA
NOP
Q3
Execute
Execute
Q4
NOP
NOP
Example:
RETFIE
After Interrupt
PC
= TOS
GLINTD = 0
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Forced NOP
Return Literal to WREG
[ label ] RETLW k
0 ≤ k ≤ 255
k → (WREG); TOS → (PC);
PCLATH is unchanged
None
1011 0110 kkkk kkkk
WREG is loaded with the eight bit literal
'k'. The program counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
1
2
Q2
Read
literal 'k'
NOP
Q3
Execute
Execute
Q4
Write to
WREG
NOP
Example:
CALL TABLE ; WREG contains table
; offset value
; WREG now has
; table value
:
TABLE
ADDWF PC ; WREG = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
WREG = 0x07
After Instruction
WREG = value of k7
© 1996 Microchip Technology Inc.
DS30412C-page 131