PIC17C44 Datasheet, PDF (232/241 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
Figure 6-12: Program Counter using The CALL and
GOTO Instructions...................................... 41
Figure 6-13: BSR Operation (PIC17C43/R43/44) ........... 42
Figure 7-1: TLWT Instruction Operation........................ 43
Figure 7-2: TABLWT Instruction Operation................... 43
Figure 7-3: TLRD Instruction Operation ........................ 44
Figure 7-4: TABLRD Instruction Operation ................... 44
Figure 7-5: TABLWT Write Timing
(External Memory) ...................................... 46
Figure 7-6: Consecutive TABLWT Write Timing
(External Memory) ...................................... 47
Figure 7-7: TABLRD Timing.......................................... 48
Figure 7-8: TABLRD Timing (Consecutive TABLRD
Instructions) ................................................ 48
Figure 9-1: RA0 and RA1 Block Diagram ..................... 53
Figure 9-2: RA2 and RA3 Block Diagram ..................... 54
Figure 9-3: RA4 and RA5 Block Diagram ..................... 54
Figure 9-4: Block Diagram of RB<7:4> and RB<1:0>
Port Pins ..................................................... 55
Figure 9-5: Block Diagram of RB3 and RB2 Port Pins.. 56
Figure 9-6: Block Diagram of RC<7:0> Port Pins ......... 58
Figure 9-7: PORTD Block Diagram
(in I/O Port Mode) ....................................... 60
Figure 9-8: PORTE Block Diagram
(in I/O Port Mode) ....................................... 62
Figure 9-9: Successive I/O Operation ........................... 64
Figure 11-1: T0STA Register (Address: 05h,
Unbanked) .................................................. 67
Figure 11-2: Timer0 Module Block Diagram ................... 68
Figure 11-3: TMR0 Timing with External Clock
(Increment on Falling Edge) ....................... 68
Figure 11-4: TMR0 Timing: Write High or Low Byte ....... 69
Figure 11-5: TMR0 Read/Write in Timer Mode ............... 70
Figure 12-1: TCON1 Register (Address: 16h, Bank 3) ... 71
Figure 12-2: TCON2 Register (Address: 17h, Bank 3) ... 72
Figure 12-3: Timer1 and Timer2 in Two 8-bit
Timer/Counter Mode................................... 73
Figure 12-4: TMR1 and TMR2 in 16-bit Timer/Counter
Mode........................................................... 74
Figure 12-5: Simplified PWM Block Diagram .................. 75
Figure 12-6: PWM Output ............................................... 75
Figure 12-7: Timer3 with One Capture and One
Period Register Block Diagram................... 78
Figure 12-8: Timer3 with Two Capture Registers
Block Diagram ............................................ 79
Figure 12-9: TMR1, TMR2, and TMR3 Operation in
External Clock Mode................................... 80
Figure 12-10: TMR1, TMR2, and TMR3 Operation in
Timer Mode................................................. 81
Figure 13-1: TXSTA Register (Address: 15h, Bank 0) .... 83
Figure 13-2: RCSTA Register (Address: 13h, Bank 0) ... 84
Figure 13-3: USART Transmit......................................... 85
Figure 13-4: USART Receive.......................................... 85
Figure 13-5: Asynchronous Master Transmission........... 90
Figure 13-6: Asynchronous Master Transmission
(Back to Back) ............................................ 90
Figure 13-7: RX Pin Sampling Scheme .......................... 91
Figure 13-8: Asynchronous Reception............................ 92
Figure 13-9: Synchronous Transmission ........................ 94
Figure 13-10: Synchronous Transmission
(Through TXEN) ......................................... 94
Figure 13-11: Synchronous Reception (Master Mode,
SREN)......................................................... 95
Figure 14-1: Configuration Word..................................... 99
Figure 14-2: Crystal or Ceramic Resonator Operation
(XT or LF OSC Configuration) .................. 100
Figure 14-3: Crystal Operation, Overtone Crystals
(XT OSC Configuration) ........................... 101
Figure 14-4: External Clock Input Operation
(EC OSC Configuration)........................... 101
Figure 14-5: External Parallel Resonant Crystal
Oscillator Circuit ....................................... 102
Figure 14-6: External Series Resonant Crystal
Oscillator Circuit ....................................... 102
Figure 14-7: RC Oscillator Mode .................................. 102
Figure 14-8: Watchdog Timer Block Diagram............... 104
Figure 14-9: Wake-up From Sleep Through Interrupt... 105
Figure 15-1: General Format for Instructions................ 108
Figure 15-2: Q Cycle Activity ........................................ 109
Figure 17-1: Parameter Measurement Information....... 154
Figure 17-2: External Clock Timing .............................. 155
Figure 17-3: CLKOUT and I/O Timing .......................... 156
Figure 17-4: Reset, Watchdog Timer,
Oscillator Start-Up Timer and
Power-Up Timer Timing ........................... 157
Figure 17-5: Timer0 Clock Timings............................... 158
Figure 17-6: Timer1, Timer2, And Timer3 Clock
Timings..................................................... 158
Figure 17-7: Capture Timings ....................................... 159
Figure 17-8: PWM Timings ........................................... 159
Figure 17-9: USART Module: Synchronous
Transmission (Master/Slave) Timing ........ 160
Figure 17-10: USART Module: Synchronous Receive
(Master/Slave) Timing .............................. 160
Figure 17-11: Memory Interface Write Timing ................ 161
Figure 17-12: Memory Interface Read Timing ................ 162
Figure 18-1: Typical RC Oscillator Frequency
vs. Temperature ....................................... 163
Figure 18-2: Typical RC Oscillator Frequency
vs. VDD ..................................................... 164
Figure 18-3: Typical RC Oscillator Frequency
vs. VDD ..................................................... 164
Figure 18-4: Typical RC Oscillator Frequency
vs. VDD ..................................................... 165
Figure 18-5: Transconductance (gm) of LF Oscillator
vs. VDD ..................................................... 166
Figure 18-6: Transconductance (gm) of XT Oscillator
vs. VDD ..................................................... 166
Figure 18-7: Typical IDD vs. Frequency (External
Clock 25°C) .............................................. 167
Figure 18-8: Maximum IDD vs. Frequency (External
Clock 125°C to -40°C) .............................. 167
Figure 18-9: Typical IPD vs. VDD Watchdog
Disabled 25°C .......................................... 168
Figure 18-10: Maximum IPD vs. VDD Watchdog
Disabled ................................................... 168
Figure 18-11: Typical IPD vs. VDD Watchdog
Enabled 25°C ........................................... 169
Figure 18-12: Maximum IPD vs. VDD Watchdog
Enabled .................................................... 169
Figure 18-13: WDT Timer Time-Out Period vs. VDD ...... 170
Figure 18-14: IOH vs. VOH, VDD = 3V.............................. 170
Figure 18-15: IOH vs. VOH, VDD = 5V.............................. 171
Figure 18-16: IOL vs. VOL, VDD = 3V............................... 171
Figure 18-17: IOL vs. VOL, VDD = 5V............................... 172
Figure 18-18: VTH (Input Threshold Voltage) of
I/O Pins (TTL) VS. VDD ............................. 172
Figure 18-19: VTH, VIL of I/O Pins (Schmitt Trigger) VS.
VDD ........................................................... 173
Figure 18-20: VTH (Input Threshold Voltage) of OSC1
Input (In XT and LF Modes) vs. VDD ........ 173
Figure 19-1: Parameter Measurement Information....... 183
DS30412C-page 232
© 1996 Microchip Technology Inc.