PIC17C44 Datasheet, PDF (126/241 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
MOVFP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Move f to p
[label] MOVFP f,p
0 ≤ f ≤ 255
0 ≤ p ≤ 31
(f) → (p)
None
011p pppp ffff ffff
Move data from data memory location 'f'
to data memory location 'p'. Location 'f'
can be anywhere in the 256 word data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Either ’p' or 'f' can be WREG (a useful
special situation).
MOVFP is particularly useful for transfer-
ring a data memory location to a periph-
eral register (such as the transmit buffer
or an I/O port). Both 'f' and 'p' can be
indirectly addressed.
1
1
Q2
Read
register 'f'
Q3
Execute
Q4
Write
register 'p'
Example:
MOVFP REG1, REG2
Before Instruction
REG1
=
REG2
=
0x33,
0x11
After Instruction
REG1
=
REG2
=
0x33,
0x33
MOVLB
Move Literal to low nibble in BSR
Syntax:
[ label ] MOVLB k
Operands:
0 ≤ k ≤ 15
Operation:
k → (BSR<3:0>)
Status Affected: None
Encoding:
1011 1000 uuuu kkkk
Description:
The four bit literal 'k' is loaded in the
Bank Select Register (BSR). Only the
low 4-bits of the Bank Select Register
are affected. The upper half of the BSR
is unchanged. The assembler will
encode the “u” fields as '0'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
literal 'u:k'
Q3
Execute
Q4
Write literal
'k' to
BSR<3:0>
Example:
MOVLB 0x5
Before Instruction
BSR register = 0x22
After Instruction
BSR register = 0x25
Note:
For the PIC17C42, only the low four bits of
the BSR register are physically imple-
mented. The upper nibble is read as '0'.
DS30412C-page 126
© 1996 Microchip Technology Inc.