PIC17C44 Datasheet, PDF (46/241 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
7.2 Table Writes to External Memory
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
Note:
If an interrupt is pending or occurs during
the TABLWT, the two cycle table write
completes. The RA0/INT, TMR0, or T0CKI
interrupt flag is automatically cleared or
the pending peripheral interrupt is
acknowledged.
7.2.2 TABLE WRITE CODE
The “i” operand of the TABLWT instruction can specify
that the value in the 16-bit TBLPTR register is auto-
matically incremented for the next write. In
Example 7-1, the TBLPTR register is not automatically
incremented.
EXAMPLE 7-1: TABLE WRITE
CLRWDT
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
MOVLW
TABLWT
; Clear WDT
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
; address
LOW (TBL_ADDR) ;
TBLPTRL
;
HIGH (DATA)
; Load HI byte
1, WREG
; in TABLATCH
LOW (DATA)
; Load LO byte
0,0,WREG
; in TABLATCH
; and write to
; program memory
; (Ext. SRAM)
FIGURE 7-5: TABLWT WRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
PC+1
TBL
Data out PC+2
Instruction
fetched
Instruction
executed
TABLWT
INST (PC+1)
INST (PC-1)
TABLWT cycle1 TABLWT cycle2
Data write cycle
ALE
OE
'1'
WR
INST (PC+2)
INST (PC+1)
Note: If external write GLINTD = '1', Enable bit = '1', '1' → Flag bit, Do table write. The highest pending interrupt is cleared.
DS30412C-page 46
© 1996 Microchip Technology Inc.