PIC17C44 Datasheet, PDF (125/241 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Inclusive OR WREG with f
[ label ] IORWF f,d
0 ≤ f ≤ 255
d ∈ [0,1]
(WREG) .OR. (f) → (dest)
Z
0000 100d ffff ffff
Inclusive OR WREG with register 'f'. If
'd' is 0 the result is placed in WREG. If
'd' is 1 the result is placed back in regis-
ter 'f'.
1
1
Q2
Read
register 'f'
Q3
Execute
Q4
Write to
destination
Example:
IORWF RESULT, 0
Before Instruction
RESULT = 0x13
WREG = 0x91
After Instruction
RESULT = 0x13
WREG = 0x93
LCALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Forced NOP
Long Call
[ label ] LCALL k
0 ≤ k ≤ 255
PC + 1 → TOS;
k → PCL, (PCLATH) → PCH
None
1011 0111 kkkk kkkk
LCALL allows an unconditional subrou-
tine call to anywhere within the 64k pro-
gram memory space.
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit desti-
nation address is then loaded into the
program counter. The lower 8-bits of
the destination address is embedded in
the instruction. The upper 8-bits of PC
is loaded from PC high holding latch,
PCLATH.
1
2
Q2
Read
literal 'k'
NOP
Q3
Execute
Execute
Q4
Write
register PCL
NOP
Example:
MOVLW HIGH(SUBROUTINE)
MOVPF WREG, PCLATH
LCALL LOW(SUBROUTINE)
Before Instruction
SUBROUTINE =
PC
=
16-bit Address
?
After Instruction
PC
= Address (SUBROUTINE)
© 1996 Microchip Technology Inc.
DS30412C-page 125