PIC18FXXK80 Datasheet, PDF (9/52 Pages) Microchip Technology – Flash Microcontroller Programming Specification

PIC18FXXK80 FAMILY
In addition to the code memory space, there are three
blocks in the configuration and ID space that are
accessible to the user through table reads and table
writes. Their locations in the memory map are shown in
Figure 2-8.
Users may store Identification (ID) information in eight
ID registers. These ID registers are mapped in
addresses, 200000h through 200007h. The ID loca-
tions read out normally, even after code protection is
applied.
Locations, 300000h through 30000Dh, are reserved for
the Configuration bits. These bits select various device
options and are described in Section 5.0 “Configura-
tion Word”. These Configuration bits read out normally,
even after code protection.
Locations, 3FFFFEh and 3FFFFFh, are reserved for the
Device ID bits. These bits may be used by the program-
mer to identify what device type is being programmed
and are described in Section 5.0 “Configuration
Word”. These Device ID bits read out normally, even
after code protection.
2.4.1 MEMORY ADDRESS POINTER
Memory in the address space, 0000000h to 3FFFFFh,
is addressed via the Table Pointer register, which is
comprised of three Pointer registers:
• TBLPTRU, at RAM address 0FF8h
• TBLPTRH, at RAM address 0FF7h
• TBLPTRL, at RAM address 0FF6h
TBLPTRU
Addr<21:16>
TBLPTRH
Addr<15:8>
TBLPTRL
Addr<7:0>
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.
 2011 Microchip Technology Inc.
DS39972B-page 9