PIC18FXXK80 Datasheet, PDF (38/52 Pages) Microchip Technology – Flash Microcontroller Programming Specification

PIC18FXXK80 FAMILY
TABLE 5-3: PIC18FXXK80 FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
DEBUG
BBSIZ⁽¹⁾
STVREN
CP3
CP2
CP1
CP0
CPD
CPB
WRT3
WRT2
WRT1
WRT0
WRTD
WRTB
WRTC
EBTR3
Note 1:
2:
3:
CONFIG4L
Background Debugger Enable bit
1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose
I/O pins
0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit Debug
CONFIG4L
Boot Block Size Select bit
1 = 2K word Boot Block size
0 = 1K word Boot Block size
CONFIG4L
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow is enabled
0 = Reset on stack overflow/underflow is disabled
CONFIG5L
Code Protection bit (Block 3 code memory area)
1 = Block 3 is not code-protected
0 = Block 3 is code-protected
CONFIG5L
Code Protection bit (Block 2 code memory area)
1 = Block 2 is not code-protected
0 = Block 2 is code-protected
CONFIG5L
Code Protection bit (Block 1 code memory area)
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
CONFIG5L
Code Protection bit (Block 0 code memory area)
1 = Block 0 is not code-protected
0 = Block 0 is code-protected
CONFIG5H
Code Protection bit (Data EEPROM)
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
CONFIG5H
Code Protection bit (Boot Block memory area)
1 = Boot Block is not code-protected
0 = Boot Block is code-protected
CONFIG6L
Write Protection bit (Block 3 code memory area)
1 = Block 3 is not write-protected
0 = Block 3 is write-protected
CONFIG6L
Write Protection bit (Block 2 code memory area)
1 = Block 2 is not write-protected
0 = Block 2 is write-protected
CONFIG6L
Write Protection bit (Block 1 code memory area)
1 = Block 1 is not write-protected
0 = Block 1 is write-protected
CONFIG6L
Write Protection bit (Block 0 code memory area)
1 = Block 0 is not write-protected
0 = Block 0 is write-protected
CONFIG6H
Write Protection bit (Data EEPROM)
1 = Data EEPROM is not write-protected
0 = Data EEPROM is write-protected
CONFIG6H
Write Protection bit (Boot Block memory area)
1 = Boot Block is not write-protected
0 = Boot Block is write-protected
CONFIG6H
Write Protection bit (Configuration registers)
1 = Configuration registers are not write-protected
0 = Configuration registers are write-protected
CONFIG7L
Table Read Protection bit (Block 3 code memory area)
1 = Block 3 is not protected from table reads executed in other blocks
0 = Block 3 is protected from table reads executed in other blocks
The BBSIZ bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or
WRT0, EBTRB or EBTR0.
Available on PIC18F6XKXX devices only.
This bit must be maintained as ‘0’ on 28-pin PIC18F2XK80 and 40-pin PIC18F4XK80 devices.
DS39972B-page 38
 2011 Microchip Technology Inc.