PIC18FXXK80 Datasheet, PDF (19/52 Pages) Microchip Technology – Flash Microcontroller Programming Specification

PIC18FXXK80 FAMILY
FIGURE 3-2:
BLOCK ERASE TIMING
12 3 4
PGC
12
P5
15 16 1 2 3 4
12
P5A
P5
15 16 1 2 3 4
P5A
P10
12
P11
PGD 0 0 1 1
11 00
00 00
00 00
0 0 00
4-Bit Command
16-Bit
Data Payload
4-Bit Command
16-Bit
4-Bit Command
Data Payload
PGD = Input
Erase Time
nn
16-Bit
Data Payload
3.1.2 ICSP ROW ERASE
It is possible to erase one row (64 bytes of data)
provided the block is not code or write-protected. Rows
are located at static boundaries beginning at program
memory address, 000000h, extending to the internal
program memory limit (see Section 2.4 “Memory
Maps”).
The Row Erase duration is externally timed and is
controlled by PGC. After the WR bit in EECON1 is set,
a NOP is issued, where the 4th PGC is held high for the
duration of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by Parameter P10 to allow high-voltage
discharge of the memory array.
The code sequence to Row Erase a PIC18FXXK80
family device is shown in Table 3-9. The flowchart
shown in Figure 3-3 depicts the logic necessary to
completely erase a PIC18FXXK80 family device. The
timing diagram that details the Start Programming
command and Parameters P9 and P10 is shown in
Figure 3-4.
Note: The TBLPTR register can point to any
byte within the row intended for erase.
 2011 Microchip Technology Inc.
DS39972B-page 19