PIC18FXXK80 Datasheet, PDF (37/52 Pages) Microchip Technology – Flash Microcontroller Programming Specification

PIC18FXXK80 FAMILY
TABLE 5-3: PIC18FXXK80 FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
BOREN<1:0>
CONFIG2L
Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset is enabled in hardware only and disabled in Sleep mode
(SBOREN is disabled)
01 = Brown-out Reset is enabled and controlled by software (SBOREN is enabled)
00 = Brown-out Reset is disabled in hardware and software
PWRTEN
CONFIG2L
Power-up Timer Enable bit
1 = PWRT is disabled
0 = PWRT is enabled
WDTPS<4:0>
CONFIG2H
Watchdog Timer Postscale Select bits
10101-11111: Reserved
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32,768
01110 = 1:16,384
01101 = 1:8,192
01100 = 1:4,096
01011 = 1:2,048
01010 = 1:1,024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
WDTEN<1:0>
CONFIG2H
Watchdog Timer Enable bits
11 = WDT is enabled in hardware; SWDTEN bit is disabled
10 = WDT is controlled with the SWDTEN bit setting
01 = WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is
disabled
00 = WDT is disabled in hardware; SWDTEN bit is disabled
MCLRE
CONFIG3H
MCLR Pin Enable bit
1 = MCLR pin is enabled, RE3 input pin is disabled
0 = RE3 input pin is enabled, MCLR pin is disabled
MSSPMSK
T3CKMX^(2,3)
T0CKMX⁽²⁾
CONFIG3H
CONFIG3H
CONFIG3H
MSSP V3 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
Timer3 Clock Input MUX bit
1 = Timer3 gets its clock input from the T1CKI input when T3CON(SOSCEN) = 0
0 = Timer3 gets its clock input from the T3CKI input when T3CON(SOSCEN) = 0
Timer0 Clock Input MUX bit
1 = Timer0 gets its clock input from the RB5/T0CKI pin
0 = Timer0 gets its clock input from the RG4/T0CKI pin
CANMX
CONFIG3H
ECAN MUX bit
1 = ECAN TX and RX pins are located on RB2 and RB3, respectively
0 = ECAN TX and RX pins are located on RC6 and RC7, respectively (28-pin and 44-pin
packages) or on RE5 and RE4, respectively (64-pin package)
Note 1:
2:
3:
The BBSIZ bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or
WRT0, EBTRB or EBTR0.
Available on PIC18F6XKXX devices only.
This bit must be maintained as ‘0’ on 28-pin PIC18F2XK80 and 40-pin PIC18F4XK80 devices.
 2011 Microchip Technology Inc.
DS39972B-page 37