PIC18FXXK80 Datasheet, PDF (33/52 Pages) Microchip Technology – Flash Microcontroller Programming Specification

PIC18FXXK80 FAMILY
FIGURE 4-4:
SHIFT OUT DATA HOLDING REGISTER TIMING (‘0010’)
PGC
1234
12 345 6 78
9 10 11 12 13 14 15 16
12 34
P5
P6
P5A
P14
PGD
0100
PGD = Input
LSb 1 2 3 4 5 6 MSb n n n n
Shift Data Out
PGD = Output
Fetch Next 4-Bit Command
PGD = Input
4.5 Verify Data EEPROM
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (TABLAT
register). The result may then be immediately com-
pared to the appropriate data in the programmer’s
memory for verification. Refer to Section 4.4 “Read
Data EEPROM Memory” for implementation details of
reading data EEPROM.
4.6 Blank Check
The term, “Blank Check”, means to verify that the device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The Device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as a ‘1’. So,
Blank Checking a device merely means to verify that all
bytes read as FFh, except the Configuration bits.
Unused (reserved) Configuration bits will read ‘0’ (pro-
grammed). Refer to Table 5-1 for blank configuration
expect data for the various PIC18FXXK80 family
devices.
Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.4 “Read Data EEPROM Memory” and
Section 4.2 “Verify Code Memory and ID Locations”
for implementation details.
FIGURE 4-5:
BLANK CHECK FLOW
Start
Blank Check Device
Is
device
blank?
No
Abort
Yes
Continue
 2011 Microchip Technology Inc.
DS39972B-page 33