PIC18FXXK80 Datasheet, PDF (16/52 Pages) Microchip Technology – Flash Microcontroller Programming Specification

PIC18FXXK80 FAMILY
3.1 ICSP Erase
3.1.1 ICSP BLOCK ERASE
Erasing code or data EEPROM is accomplished by config-
uring three Block Erase Control registers, located at
3C0004h through 3C0006h. Code memory can only be
erased, portions at a time. In order to erase the entire
device, every block must be erased sequentially. Block
Erase operations will also clear any code-protect settings
associated with the memory block being erased. Erase
options are detailed in Table 3-1. Data EEPROM is
erased at the same time as all Block Erase commands.
In order to erase data EEPROM by itself, the first code
sequence in Table 3-1 must be used. If the entire device
is being erased, this code is not necessary.
TABLE 3-1: BLOCK ERASE OPERATIONS
Description
Data
(3C0006h:3C0004h)
Erase Data EEPROM
Erase Boot Block
Erase Config Bits
Erase Code EEPROM Block 0
Erase Code EEPROM Block 1
Erase Code EEPROM Block 2
Erase Code EEPROM Block 3
800004h
800005h
800002h
800104h
800204h
800404h
800804h
The actual Block Erase function is a self-timed operation.
Once the erase has started (falling edge of the 4th PGC
after the NOP command), serial execution will cease until
the erase completes (Parameter P11). During this time,
PGC may continue to toggle, but PGD must be held low.
The code sequence to erase the entire device is shown
in Table 3-2 through Table 3-7 and the flowchart is
shown in Figure 3-1. The code sequence to just erase
data EEPROM is shown in Table 3-8.
Note:
A Block Erase is the only way to repro-
gram code-protect bits from an ON state
to an OFF state.
TABLE 3-2: ERASE BLOCK 0
4-Bit
Data
Command Payload
Core Instruction
0000
0000
0000
0000
0000
0000
1100
0000
0000
1100
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
04 04
0E 05
6E F6
01 01
0E 06
6E F6
80 80
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 04h to 3C0004h
MOVLW 05h
MOVWF TBLPTRL
Write 01h to 3C0005h
MOVLW 06h
MOVWF TBLPTRL
Write 80h to 3C0006h to
erase block 0
NOP
Hold PGD low until erase
completes
TABLE 3-3: ERASE BLOCK 1
4-Bit
Data
Command Payload
Core Instruction
0000
0000
0000
0000
0000
0000
1100
0000
0000
1100
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
04 04
0E 05
6E F6
02 02
0E 06
6E F6
80 80
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 04h to 3C0004h
MOVLW 05h
MOVWF TBLPTRL
Write 02h to 3C0005h
MOVLW 06h
MOVWF TBLPTRL
Write 80h to 3c0006h to
erase block 1
NOP
Hold PGD low until
erase completes
TABLE 3-4: ERASE BLOCK 2
4-Bit
Data
Command Payload
Core Instruction
0000
0000
0000
0000
0000
0000
1100
0000
0000
1100
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
04 04
0E 05
6E F6
04 04
0E 06
6E F6
80 80
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 04h to 3C0004h
MOVLW 05h
MOVWF TBLPTRL
Write 04h to 3C0005h
MOVLW 06h
MOVWF TBLPTRL
Write 80h to 3C0006h to
erase block 2
NOP
Hold PGD low until
erase completes
DS39972B-page 16
 2011 Microchip Technology Inc.