PIC18FXXK80 Datasheet, PDF (26/52 Pages) Microchip Technology – Flash Microcontroller Programming Specification

PIC18FXXK80 FAMILY
3.3 Data EEPROM Programming
Data EEPROM is accessed, one byte at a time, via an
Address Pointer (register pair, EEADRH:EEADR) and
a Data Latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA with the data to be written and
initiating a memory write by appropriately configuring
the EECON1 register (Register 3-1). A byte write auto-
matically erases the location and writes the new data
(erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC must
still be held low for the time specified by Parameter P10
to allow high-voltage discharge of the memory array.
FIGURE 3-7:
PROGRAM DATA FLOW
Start
Set Address
Set Data
Enable Write
Start Write
Sequence
WR bit
No
clear?
Yes
No
Done?
Yes
Done
FIGURE 3-8:
DATA EEPROM WRITE TIMING
12 3 4
12
PGC
P5
15 16
P5A
PGD ^{0 0 0 0}
4-Bit Command BSF EECON1, WR
P11A
Poll WR Bit, Repeat until Clear
(see below)
PGD = Input
P10
12
nn
16-Bit Data
Payload
PGC
Poll WR bit
PGD
12 3 4
1 2 15 16 1 2 3 4
1 2 15 16
P5
P5A
P5
P5A
0000
0000
4-Bit Command MOVF EECON1, W, 0 4-Bit Command MOVWF TABLAT
PGD = Input
Shift Out Data
(see Figure 4-4)
PGD = Output
DS39972B-page 26
 2011 Microchip Technology Inc.