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RFPIC12F675 Datasheet, PDF (8/136 Pages) Microchip Technology – FLASH-Based Microcontroller with ASK/FSK Transmitter
rfPIC12F675
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Page
Bank 1
80h
INDF(1)
Addressing this Location uses Contents of FSR to Address Data Memory
0000 0000 16,63
81h
OPTION_REG GPPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 10,26
82h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 15
83h
STATUS
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
0001 1xxx 9
84h
FSR
Indirect Data Memory Address Pointer
xxxx xxxx 16
85h
TRISIO
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 17
86h
—
Unimplemented
—
—
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah
PCLATH
—
—
—
Write Buffer for Upper 5 bits of Program Counter
---0 0000 15
8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF 0000 0000 11
8Ch
PIE1
EEIE
ADIE
—
—
CMIE
—
—
TMR1IE 00-- 0--0 12
8Dh
—
Unimplemented
—
—
8Eh
PCON
—
—
—
—
—
—
POR
BOD ---- --0x 14
8Fh
—
Unimplemented
—
—
90h
OSCCAL
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
1000 00-- 14
91h
—
Unimplemented
—
—
92h
—
Unimplemented
—
—
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
WPU
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0 --11 -111 18
96h
IOC
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0 --00 0000 19
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
VRCON
VREN
—
VRR
—
VR3
VR2
VR1
VR0 0-0- 0000 38
9Ah
EEDATA
Data EEPROM Data Register
0000 0000 45
9Bh
EEADR
—
Data EEPROM Address Register
-000 0000 45
9Ch
EECON1
—
—
—
9Dh
EECON2(1)
EEPROM Control Register 2
—
WRERR WREN
WR
RD
---- x000 46
---- ---- 46
9Eh
ADRESL
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result
xxxx xxxx 40
9Fh
ANSEL
—
ADCS2 ADCS1 ADCS0
ANS3
ANS2
ANS1
ANS0 -000 1111 42,63
Legend:
Note 1:
2:
— = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
This is not a physical register.
These bits are reserved and should always be maintained as ‘0’.
DS70091B-page 8
Preliminary
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