RFPIC12F675 Datasheet, PDF (53/136 Pages) Microchip Technology – FLASH-Based Microcontroller with ASK/FSK Transmitter

9.6 Clock Output
The clock output is available to the microcontroller or
other circuits requiring an accurate reference
frequency. This signal would typically be used to
correct the internal RC oscillator for system designs
that require accurate bit synchronization or tight time
division multiplexing. The REFCLK output can
connect directly to the T0CKI or T1CKI.
The REFCLK output frequency is the crystal oscillator
divided by 4 on the rfPIC12F675K and rfPIC12F675F.
For the rfPIC12F675H the crystal oscillator is divided
by 8.
Layout considerations - Keep the clock trace short
and narrow yet as far as possible from other traces to
reduce capacitance and the associated current draw.
If the REFCLK trace must pass near the crystal and
LF nodes then shield them with ground traces.
9.7 Phase-Locked Loop Filter
The LF pin connects to an internal node on the PLL
filter. Typically the pin should not be connected. In
specialized cases it may be necessary to load this pin
with extra capacitance to ground. Adding capacitance
reduces the loop filter bandwidth which trades off an
increase in phase noise for a reduction in clock spurs.
Useful diagnostic measurements can be taken on the
LF pin with a high impedance, low capacitance probe.
Measuring the time from RFEN going high until the LF
voltage stabilizes will determine the minimum delay
before the start of a transmission. For more information
on PLL filters refer to Application Note AN846 Basic
PLL Filters for the rfPIC™/rfHCS.
Layout considerations - Keep traces short and if the
optional loop filter capacitor is required, place it as
close as possible to the LF pin with its own via to the
ground plane.
rfPIC12F675
9.8 Power Amplifier
The PLL output feeds the power amplifier (PA) which
drives the open-collector ANT output. The output
should be DC biased with an inductor to the VDDRF
supply. The output impedance must be matched to the
load impedance to deliver the maximum power. This is
typically done with a transformer or tapped capacitor
circuit. Failure to match the impedance may cause
excessive spurious and harmonic emissions. For more
information on transformer matching see Application
Note AN831, Matching Small Loop Antennas to rfPIC™
Devices. For more information on tapped capacitor
matching see Application Note AN242 Designing an
FCC Approved ASK rfPIC™ Transmitter.
The transmit output power can be adjusted in five
discrete steps from +9 dBm to -70 dBm by varying the
voltage on the PS pin. Since the PS pin has an internal
8 A source the voltage can be set with a resistor from
the PS pin to ground as shown in Figure 9-7. Some
possible resistor values to set the current are shown in
Table 9-4.
It is usually desirable to select the lowest power level
step that does not compromise communications reli-
ablity. The most important benefit is the conservation of
battery power. Another reason is to make it easier to
pass regulatory limits. And a third reason is to reduce
interference to other communications in the shared RF
spectrum. Small inefficient antennas will require higher
power level settings than larger efficient antennas.
FIGURE 9-7: .POWER SELECT CIRCUIT
VPS
PS
R1
rfPIC12F675
IPS = 8 A
To power
select
circuitry
TABLE 9-4: POWER SELECT RESISTOR SELECTION ^(1,2)
Power Step
Output Power
(dBm)
PS Voltage
(Volts)
R1 Resistance RF Transmitter
()
Current (mA)
4
9
1.6
open
10.7
3
2
2
-4
1
-12
0
-70
0.8
100k ⁽³⁾
6.5
0.4
47k ⁽³⁾
4.7
0.2
22k ⁽³⁾
3.5
0.1
short
2.7
Note 1: Standard Operating Conditions, TA = 25°C, RFEN = 1, VDDRF = 3V, fTRANSMIT = 433.92 MHz
2: Typical values, for complete specifications see data sheet Section 13.0.
3: R1 resistor variations plus IPS current supply variations must not exceed VPS step limits.
 2003-2013 Microchip Technology Inc.
Preliminary
DS70091B-page 53