RFPIC12F675 Datasheet, PDF (61/136 Pages) Microchip Technology – FLASH-Based Microcontroller with ASK/FSK Transmitter

rfPIC12F675
10.3.5 BROWN-OUT DETECT (BOD)
The rfPIC12F675 members have on-chip Brown-out
Detect circuitry. A configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Detect circuitry. If VDD falls below VBOD for
greater than parameter (TBOD) in Table 13-4 (see
Section 13.0), the Brown-out situation will reset the
device. This will occur regardless of VDD slew-rate. A
RESET is not guaranteed to occur if VDD falls below
VBOD for less than parameter (TBOD).
FIGURE 10-6:
BROWN-OUT SITUATIONS
On any RESET (Power-on, Brown-out, Watchdog,
etc.), the chip will remain in RESET until VDD rises
above BVDD (see Figure 10-6). The Power-up Timer
will now be invoked, if enabled, and will keep the chip
in RESET an additional 72 ms.
Note:
A Brown-out Detect does not enable the
Power-up Timer if the PWRTE bit in the
configuration word is set.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-up Timer will execute a
72 ms RESET.
VDD
VBOD
Internal
RESET
72 ms⁽¹⁾
VDD
VBOD
Internal
RESET
<72 ms
72 ms⁽¹⁾
VDD
Internal
RESET
Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.
72 ms⁽¹⁾
VBOD
10.3.6 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired.
Then, OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE bit
status. For example, in EC mode with PWRTE bit
erased (PWRT disabled), there will be no time-out at
all. Figure 10-7, Figure 10-8 and Figure 10-9 depict
time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 10-8). This is useful for testing purposes or
to synchronize more than one rfPIC12F675 device
operating in parallel.
Table 10-6 shows the RESET conditions for some
special registers, while Table 10-7 shows the RESET
conditions for all the registers.
10.3.7 POWER CONTROL (PCON) STATUS
REGISTER
The power CONTROL/STATUS register, PCON
(address 8Eh) has two bits.
Bit0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent RESETS to see if BOD = 0, indicating
that a brown-out has occurred. The BOD STATUS bit is
a don’t care and is not necessarily predictable if the
brown-out circuit is disabled (by setting BODEN bit = 0
in the Configuration word).
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent RESET, if POR is ‘0’, it will indicate that a
Power-on Reset must have occurred (i.e., VDD may
have gone too low).
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Preliminary
DS70091B-page 61