RFPIC12F675 Datasheet, PDF (13/136 Pages) Microchip Technology – FLASH-Based Microcontroller with ASK/FSK Transmitter

rfPIC12F675
2.2.2.5 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 2-5:
PIR1 — PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
R/W-0 R/W-0
U-0
U-0
R/W-0
U-0
U-0
EEIF
ADIF
—
—
CMIF
—
—
bit 7
R/W-0
TMR1IF
bit 0
bit 7
bit 6
bit 5-4
bit 3
bit 2-1
bit 0
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
ADIF: A/D Converter Interrupt Flag bit 
1 = The A/D conversion is complete (must be cleared in software)
0 = The A/D conversion is not complete
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
Unimplemented: Read as ‘0’
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
 2003-2013 Microchip Technology Inc.
Preliminary
DS70091B-page 13