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| RFPIC12F675 Datasheet, PDF (22/136 Pages) Microchip Technology – FLASH-Based Microcontroller with ASK/FSK Transmitter | |||
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rfPIC12F675
3.3.5 GP4/AN3/T1G/OSC2/CLKOUT
Figure 3-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
⢠a general purpose I/O
⢠an analog input for the A/D
⢠a TMR1 gate input
⢠a crystal/resonator connection
⢠a clock output
FIGURE 3-4:
Data Bus
DQ
WR
WPU
CK Q
RD
WPU
WR
PORT
DQ
CK Q
WR
TRISIO
DQ
CK Q
RD
TRISIO
RD
PORT
WR
IOC
DQ
CK Q
RD
IOC
Interrupt-on-Change
BLOCK DIAGRAM OF GP4
Analog
Input Mode
CLK
Modes(1)
VDD
Weak
GPPU
Oscillator
Circuit
OSC1
CLKOUT
Enable
FOSC/4 1
0
CLKOUT
Enable
INTOSC/
RC/EC(2)
CLKOUT
Enable
Analog
Input Mode
VDD
I/O pin
VSS
QD
EN
QD
EN
To TMR1 T1G
To A/D Converter
RD PORT
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
3.3.6 GP5/T1CKI/OSC1/CLKIN
Figure 3-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
⢠a general purpose I/O
⢠a TMR1 clock input
⢠a crystal/resonator connection
⢠a clock input
FIGURE 3-5:
BLOCK DIAGRAM OF GP5
Data Bus
DQ
WR
WPU
CK Q
RD
WPU
WR
PORT
DQ
CK Q
WR
TRISIO
DQ
CK Q
RD
TRISIO
RD
PORT
WR
IOC
DQ
CK Q
RD
IOC
Interrupt-on-Change
INTOSC
Mode
TMR1LPEN(1)
VDD
Weak
GPPU
Oscillator
Circuit
OSC2
VDD
INTOSC
Mode
I/O pin
VSS
(2)
QD
EN
QD
EN
RD PORT
To TMR1 or CLKGEN
Note
1: Timer1 LP Oscillator enabled
2: When using Timer1 with LP oscillator, the Schmitt
Trigger is by-passed.
DS70091B-page 22
Preliminary
ï£ 2003-2013 Microchip Technology Inc.
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