RFPIC12F675 Datasheet, PDF (11/136 Pages) Microchip Technology – FLASH-Based Microcontroller with ASK/FSK Transmitter

rfPIC12F675
2.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO port change and
external GP2/INT pin interrupts.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 2-3:
INTCON — INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0
GIE
bit 7
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
GPIE
R/W-0
T0IF
R/W-0
INTF
R/W-0
GPIF
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt
bit 3
GPIE: Port Change Interrupt Enable bit⁽¹⁾
1 = Enables the GPIO port change interrupt
0 = Disables the GPIO port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit^(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur
bit 0
GPIF: Port Change Interrupt Flag bit
1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software)
0 = None of the GP5:GP0 pins have changed state
Note 1: IOC register must also be enabled to enable an interrupt-on-change.
2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and
should be initialized before clearing T0IF bit.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
 2003-2013 Microchip Technology Inc.
Preliminary
DS70091B-page 11