PIC17C4X Datasheet, PDF (79/240 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
12.2.2 DUAL CAPTURE REGISTER MODE
This mode is selected by setting CA1/PR3. A block dia-
gram is shown in Figure 12-8. In this mode, TMR3 runs
without a period register and increments from 0000h to
FFFFh and rolls over to 0000h. The TMR3 interrupt
Flag (TMR3IF) is set on this roll over. The TMR3IF bit
must be cleared in software.
Registers PR3H/CA1H and PR3L/CA1L make a 16-bit
capture register (Capture1). It captures events on pin
RB0/CAP1. Capture mode is configured by the
CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit
(CA1IF) is set on the capture event. The corresponding
interrupt mask bit is CA1IE. The Capture1 Overflow
Status bit is CA1OVF.
The Capture2 overflow status flag bit is double buff-
ered. The master bit is set if one captured word is
already residing in the Capture2 register and another
“event” has occurred on the RB1/CA2 pin. The new
event will not transfer the TMR3 value to the capture
register which protects the previous unread capture
value. When the user reads both the high and the low
bytes (in any order) of the Capture2 register, the master
overflow bit is transferred to the slave overflow bit
(CA2OVF) and then the master bit is reset. The user
can then read TCON2 to determine the value of
CA2OVF.
The operation of the Capture1 feature is identical to
Capture2 (as described in Section 12.2.1).
FIGURE 12-8: TIMER3 WITH TWO CAPTURE REGISTERS BLOCK DIAGRAM
CA1ED1, CA1ED0
(TCON1<5:4>)
2
RB0/CAP1
Edge Select
Prescaler Select
PR3H/CA1H
Capture Enable
PR3L/CA1L
Fosc/4
0
RB5/TCLK3
1
TMR3ON
TMR3CS ^(TCON2<2>)
(TCON1<2>)
TMR3H
Capture Enable
TMR3L
RB1/CAP2
Edge Select
Prescaler Select
2
CA2ED1, CA2ED0
(TCON1<7:6>)
CA2H
CA2L
Set CA1IF
(PIR<2>)
Set TMR3IF
(PIR<6>)
Set CA2IF
(PIR<3>)
TABLE 12-5: REGISTERS ASSOCIATED WITH CAPTURE
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Value on all
Power-on other resets
Reset
(Note1)
16h, Bank 3 TCON1
CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
12h, Bank 2 TMR3L
TMR3 register; low byte
xxxx xxxx uuuu uuuu
13h, Bank 2 TMR3H
TMR3 register; high byte
xxxx xxxx uuuu uuuu
16h, Bank 1 PIR
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TXIF RCIF 0000 0010 0000 0010
17h, Bank 1 PIE
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TXIE RCIE 0000 0000 0000 0000
07h, Unbanked INTSTA
PEIF T0CKIF T0IF
INTF
PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
06h, Unbanked CPUSTA
—
—
STKAV GLINTD
TO
PD
—
— --11 11-- --11 qq--
16h, Bank 2 PR3L/CA1L Timer3 period register, low byte/capture1 register, low byte
xxxx xxxx uuuu uuuu
17h, Bank 2 PR3H/CA1H Timer3 period register, high byte/capture1 register, high byte
xxxx xxxx uuuu uuuu
14h, Bank 3 CA2L
Capture2 low byte
xxxx xxxx uuuu uuuu
15h, Bank 3 CA2H
Capture2 high byte
xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition,
shaded cells are not used by Capture.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
© 1996 Microchip Technology Inc.
DS30412C-page 79