PIC17C4X Datasheet, PDF (37/240 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
6.2.2.2 CPU STATUS REGISTER (CPUSTA)
The CPUSTA register contains the status and control
bits for the CPU. This register is used to globally
enable/disable interrupts. If only a specific interrupt is
desired to be enabled/disabled, please refer to the
INTerrupt STAtus (INTSTA) register and the Peripheral
Interrupt Enable (PIE) register. This register also indi-
cates if the stack is available and contains the
Power-down (PD) and Time-out (TO) bits. The TO, PD,
and STKAV bits are not writable. These bits are set and
cleared according to device logic. Therefore, the result
of an instruction with the CPUSTA register as destina-
tion may be different than intended.
FIGURE 6-8: CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
U-0
—
bit7
U - 0 R - 1 R/W - 1 R - 1
— STKAV GLINTD TO
bit 7-6: Unimplemented: Read as '0'
R-1
PD
U-0
—
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
- n = Value at POR reset
bit 5:
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh → 0h (stack overflow).
1 = Stack is available
0 = Stack is full, or a stack overflow may have occurred (Once this bit has been cleared by a
stack overflow, only a device reset will set this bit)
bit 4:
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can
cause an interrupt.
1 = Disable all interrupts
0 = Enables all un-masked interrupts
bit 3:
TO: WDT Time-out Status bit
1 = After power-up or by a CLRWDT instruction
0 = A Watchdog Timer time-out occurred
bit 2:
PD: Power-down Status bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1-0: Unimplemented: Read as '0'
© 1996 Microchip Technology Inc.
DS30412C-page 37