PIC17C4X Datasheet, PDF (120/240 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
If skip:
Q1
Forced NOP
Compare f with WREG,
skip if f < WREG
[ label ] CPFSLT f
0 ≤ f ≤ 255
(f) – (WREG),
skip if (f) < (WREG)
(unsigned comparison)
None
0011 0000 ffff ffff
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If the contents of 'f' < the contents of
WREG, then the fetched instruction is
discarded and an NOP is executed
instead making this a two-cycle instruc-
tion.
1
1 (2)
Q2
Read
register 'f'
Q3
Execute
Q2
NOP
Q3
Execute
Q4
NOP
Q4
NOP
Example:
HERE
NLESS
LESS
CPFSLT REG
:
:
Before Instruction
PC
=
W
=
Address (HERE)
?
After Instruction
If REG
<
PC
=
If REG
≥
PC
=
WREG;
Address (LESS)
WREG;
Address (NLESS)
DAW
Syntax:
Operands:
Operation:
Decimal Adjust WREG Register
[label] DAW f,s
0 ≤ f ≤ 255
s ∈ [0,1]
If [WREG<3:0> >9] .OR. [DC = 1] then
WREG<3:0> + 6 → f<3:0>, s<3:0>;
else
WREG<3:0> → f<3:0>, s<3:0>;
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
If [WREG<7:4> >9] .OR. [C = 1] then
WREG<7:4> + 6 → f<7:4>, s<7:4>
else
WREG<7:4> → f<7:4>, s<7:4>
C
0010 111s ffff ffff
DAW adjusts the eight bit value in
WREG resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0: Result is placed in Data
memory location 'f' and
WREG.
s = 1: Result is placed in Data
memory location 'f'.
1
1
Q2
Read
register 'f'
Q3
Execute
Q4
Write
register 'f'
and other
specified
register
Example1:
DAW REG1, 0
Before Instruction
WREG = 0xA5
REG1 = ??
C
=0
DC
=0
After Instruction
WREG =
REG1 =
C
=
DC
=
Example 2:
0x05
0x05
1
0
Before Instruction
WREG = 0xCE
REG1 = ??
C
=0
DC
=0
After Instruction
WREG =
REG1 =
C
=
DC
=
0x24
0x24
1
0
DS30412C-page 120
© 1996 Microchip Technology Inc.