PIC17C4X Datasheet, PDF (57/240 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
Example 9-1 shows the instruction sequence to initial-
ize PORTB. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized.
EXAMPLE 9-1: INITIALIZING PORTB
MOVLB 0
CLRF PORTB
MOVLW 0xCF
MOVWF DDRB
; Select Bank 0
; Initialize PORTB by clearing
; output data latches
; Value used to initialize
; data direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
TABLE 9-3: PORTB FUNCTIONS
Name
Bit Buffer Type
Function
RB0/CAP1
bit0
ST
RB1/CAP2
bit1
ST
RB2/PWM1
bit2
ST
RB3/PWM2
bit3
ST
RB4/TCLK12 bit4
ST
RB5/TCLK3
bit5
ST
RB6
bit6
ST
RB7
bit7
ST
Legend: ST = Schmitt Trigger input.
Input/Output or the RB0/CAP1 input pin. Software programmable weak pull-
up and interrupt on change features.
Input/Output or the RB1/CAP2 input pin. Software programmable weak pull-
up and interrupt on change features.
Input/Output or the RB2/PWM1 output pin. Software programmable weak
pull-up and interrupt on change features.
Input/Output or the RB3/PWM2 output pin. Software programmable weak
pull-up and interrupt on change features.
Input/Output or the external clock input to Timer1 and Timer2. Software pro-
grammable weak pull-up and interrupt on change features.
Input/Output or the external clock input to Timer3. Software programmable
weak pull-up and interrupt on change features.
Input/Output pin. Software programmable weak pull-up and interrupt on
change features.
Input/Output pin. Software programmable weak pull-up and interrupt on
change features.
TABLE 9-4: REGISTERS/BITS ASSOCIATED WITH PORTB
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
resets
(Note1)
12h, Bank 0
11h, Bank 0
PORTB PORTB data latch
DDRB Data direction register for PORTB
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
10h, Bank 0 PORTA RBPU
—
RA5
RA4
RA3
RA2 RA1/T0CKI RA0/INT 0-xx xxxx 0-uu uuuu
06h, Unbanked CPUSTA
07h, Unbanked INTSTA
16h, Bank 1 PIR
17h, Bank 1 PIE
16h, Bank 3 TCON1
—
—
PEIF T0CKIF
RBIF TMR3IF
RBIE TMR3IE
CA2ED1 CA2ED0
STKAV
T0IF
TMR2IF
TMR2IE
CA1ED1
GLINTD
INTF
TMR1IF
TMR1IE
CA1ED0
TO
PEIE
CA2IF
CA2IE
T16
PD
T0CKIE
CA1IF
CA1IE
TMR3CS
—
T0IE
TXIF
TXIE
TMR2CS
— --11 11-- --11 qq--
INTE 0000 0000 0000 0000
RCIF 0000 0010 0000 0010
RCIE 0000 0000 0000 0000
TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = Value depends on condition.
Shaded cells are not used by PORTB.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
© 1996 Microchip Technology Inc.
DS30412C-page 57