PIC17C4X Datasheet, PDF (34/240 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
TABLE 6-3: SPECIAL FUNCTION REGISTERS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
resets (3)
Unbanked
00h INDF0
01h FSR0
02h PCL
03h⁽¹⁾ PCLATH
04h ALUSTA
05h T0STA
Uses contents of FSR0 to address data memory (not a physical register)
Indirect data memory address pointer 0
Low order 8-bits of PC
Holding register for upper 8-bits of PC
FS3
FS2
FS1
FS0
OV
Z
DC
INTEDG T0SE
T0CS
PS3
PS2
PS1
PS0
---- ---- ---- ----
xxxx xxxx
0000 0000
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
C
1111 xxxx 1111 uuuu
—
0000 000- 0000 000-
06h⁽²⁾
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
—
—
STKAV GLINTD
TO
PD
—
PEIF T0CKIF T0IF
INTF
PEIE T0CKIE
T0IE
Uses contents of FSR1 to address data memory (not a physical register)
Indirect data memory address pointer 1
Working register
TMR0 register; low byte
TMR0 register; high byte
Low byte of program memory table pointer
High byte of program memory table pointer
Bank select register
—
INTE
--11 11-- --11 qq--
0000 0000
---- ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
(4)
(4)
0000 0000
0000 0000
---- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
(4)
(4)
0000 0000
Bank 0
10h _PORTA
11h DDRB
12h PORTB
13h RCSTA
14h RCREG
15h TXSTA
16h TXREG
17h SPBRG
RBPU
—
RA5
RA4
Data direction register for PORTB
PORTB data latch
SPEN RX9
SREN
CREN
Serial port receive register
CSRC TX9
TXEN
SYNC
Serial port transmit register
Baud rate generator register
RA3
—
—
RA2
FERR
—
RA1/T0CKI RA0/INT
OERR
RX9D
TRMT
TX9D
0-xx xxxx
1111 1111
xxxx xxxx
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
xxxx xxxx
0-uu uuuu
1111 1111
uuuu uuuu
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
uuuu uuuu
Bank 1
10h DDRC
11h PORTC
12h DDRD
13h PORTD
14h DDRE
Data direction register for PORTC
RC7/
AD7
RC6/
AD6
RC5/
AD5
Data direction register for PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
Data direction register for PORTE
RC4/
AD4
RD4/
AD12
RC3/
AD3
RD3/
AD11
RC2/
AD2
RD2/
AD10
RC1/
AD1
RD1/
AD9
RC0/
AD0
RD0/
AD8
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- -111 ---- -111
15h
16h
17h
Legend:
Note 1:
2:
3:
4:
5:
PORTE
—
—
—
—
—
RE2/WR RE1/OE RE0/ALE ---- -xxx ---- -uuu
PIR
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF
TXIF
RCIF 0000 0010 0000 0010
PIE
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE
TXIE
RCIE 0000 0000 0000 0000
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
The following values are for both TBLPTRL and TBLPTRH:
All PIC17C4X devices (Power-on Reset 0000 0000) and (All other resets 0000 0000)
except the PIC17C42 (Power-on Reset xxxx xxxx) and (All other resets uuuu uuuu)
The PRODL and PRODH registers are not implemented on the PIC17C42.
DS30412C-page 34
© 1996 Microchip Technology Inc.