PIC17C4X Datasheet, PDF (111/240 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
TABLE 15-2: PIC17CXX INSTRUCTION SET (Cont.’d)
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
Status
MSb
LSb ^Affected
Notes
TABLWT t,i,f Table Write
2 1010 11ti ffff ffff
None 5
TLRD
t,f Table Latch Read
1 1010 00tx ffff ffff
None
TLWT
t,f Table Latch Write
1 1010 01tx ffff ffff
None
TSTFSZ
f
Test f, skip if 0
1 (2) 0011 0011 ffff ffff
None 6,8
XORWF f,d Exclusive OR WREG with f
1 0000 110d ffff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f,b Bit Clear f
1 1000 1bbb ffff ffff
None
BSF
f,b Bit Set f
1 1000 0bbb ffff ffff
None
BTFSC
f,b Bit test, skip if clear
1 (2) 1001 1bbb ffff ffff
None 6,8
BTFSS
f,b Bit test, skip if set
1 (2) 1001 0bbb ffff ffff
None 6,8
BTG
f,b Bit Toggle f
1 0011 1bbb ffff ffff
None
LITERAL AND CONTROL OPERATIONS
ADDLW
k ADD literal to WREG
1 1011 0001 kkkk kkkk OV,C,DC,Z
ANDLW
k AND literal with WREG
1 1011 0101 kkkk kkkk
Z
CALL
k Subroutine Call
2 111k kkkk kkkk kkkk
None 7
CLRWDT — Clear Watchdog Timer
1 0000 0000 0000 0100
TO,PD
GOTO
k Unconditional Branch
2 110k kkkk kkkk kkkk
None 7
IORLW
k Inclusive OR literal with WREG
1 1011 0011 kkkk kkkk
Z
LCALL
k Long Call
2 1011 0111 kkkk kkkk
None 4,7
MOVLB
k Move literal to low nibble in BSR
1 1011 1000 uuuu kkkk
None
MOVLR
k Move literal to high nibble in BSR
1 1011 101x kkkk uuuu
None 9
MOVLW k Move literal to WREG
1 1011 0000 kkkk kkkk
None
MULLW
k Multiply literal with WREG
1 1011 1100 kkkk kkkk
None 9
RETFIE
— Return from interrupt (and enable interrupts)
2 0000 0000 0000 0101
GLINTD 7
RETLW
k Return literal to WREG
2 1011 0110 kkkk kkkk
None 7
RETURN — Return from subroutine
2 0000 0000 0000 0010
None 7
SLEEP
— Enter SLEEP Mode
1 0000 0000 0000 0011
TO, PD
SUBLW
k Subtract WREG from literal
1 1011 0010 kkkk kkkk OV,C,DC,Z
XORLW
k Exclusive OR literal with WREG
1 1011 0100 kkkk kkkk
Z
Legend: Refer to Table 15-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working
register (WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into
the LSB of the PC (PCL)
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruc-
tion is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruc-
tion.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
9: These instructions are not available on the PIC17C42.
© 1996 Microchip Technology Inc.
DS30412C-page 111