PIC17C4X Datasheet, PDF (16/240 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM/ROM Microcontroller

PIC17C4X
4.1.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (1024TOSC) delay after MCLR is
detected high or a wake-up from SLEEP event occurs.
The OST time-out is invoked only for XT and LF oscilla-
tor modes on a Power-on Reset or a Wake-up from
SLEEP.
The OST counts the oscillator pulses on the
OSC1/CLKIN pin. The counter only starts incrementing
after the amplitude of the signal reaches the oscillator
input thresholds. This delay allows the crystal oscillator
or resonator to stabilize before the device exits reset.
The length of time-out is a function of the crystal/reso-
nator frequency.
4.1.4 TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST
and PWRT timers start. In general the PWRT time-out
is longer, except with low frequency crystals/resona-
tors. The total time-out also varies based on oscillator
configuration. Table 4-1 shows the times that are asso-
ciated with the oscillator configuration. Figure 4-2 and
Figure 4-3 display these time-out sequences.
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/VPP pin must be
held low until the voltage is within the device specifica-
tion. The use of an external RC delay is sufficient for
many of these applications.
TABLE 4-1: TIME-OUT IN VARIOUS
SITUATIONS
Oscillator
Configuration
Power-up
XT, LF
EC, RC
Greater of:
96 ms or
1024TOSC
Greater of:
96 ms or
1024TOSC
Wake up
from
SLEEP
1024TOSC
—
MCLR
Reset
—
—
The time-out sequence begins from the first rising edge
of MCLR.
Table 4-3 shows the reset conditions for some special
registers, while Table 4-4 shows the initialization condi-
tions for all the registers. The shaded registers (in
Table 4-4) are for all devices except the PIC17C42. In
the PIC17C42, the PRODH and PRODL registers are
general purpose RAM.
TABLE 4-2: STATUS BITS AND THEIR
SIGNIFICANCE
TO PD
Event
1 1 Power-on Reset, MCLR Reset during normal
operation, or CLRWDT instruction executed
1 0 MCLR Reset during SLEEP or interrupt wake-up
from SLEEP
0 1 WDT Reset during normal operation
0 0 WDT Reset during SLEEP
TABLE 4-3:
In Figure 4-2, Figure 4-3 and Figure 4-4, TPWRT >
TOST, as would be the case in higher frequency crys-
tals. For lower frequency crystals, (i.e., 32 kHz) TOST
would be greater.
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
Event
PCH:PCL
CPUSTA
OST Active
Power-on Reset
0000h
--11 11--
Yes
MCLR Reset during normal operation
0000h
--11 11--
No
MCLR Reset during SLEEP
0000h
--11 10--
Yes ⁽²⁾
WDT Reset during normal operation
0000h
--11 01--
No
WDT Reset during SLEEP ⁽³⁾
0000h
--11 00--
Yes ⁽²⁾
Interrupt wake-up from SLEEP GLINTD is set
PC + 1
--11 10--
Yes ⁽²⁾
GLINTD is clear
PC + 1 ⁽¹⁾
--10 10--
Yes ⁽²⁾
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
then executed.
2: The OST is only active when the Oscillator is configured for XT or LF modes.
3: The Program Counter = 0, that is the device branches to the reset vector. This is different from the
mid-range devices.
DS30412C-page 16
© 1996 Microchip Technology Inc.