LAN8810I-AKZE Datasheet, PDF (76/100 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support

GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
4.3.9 CRC Error Counter Low Register
Index:
U7
Size:
16 bits
BITS
15:0
DESCRIPTION
CRCERR[15:0]
Counts the CRC errors, which are generated by the CRC checker circuit.
Contains the 16 low-order bits of the 48-bit counter.
TYPE
RO
DEFAULT
0000h
Note:
The 48-bit CRC error counter is split across 3 registers. In order to read the counter correctly,
the registers must be read in the following order: CRC Error Counter Low Register, CRC Error
Counter Mid Register, CRC Error Counter High Register. After reading the high register, the
counter will be automatically cleared.
Revision 1.0 (02-06-13)
76
DATASHEET
SMSC LAN8810/LAN8810i