LAN8810I-AKZE Datasheet, PDF (39/100 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support

GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
3.9.9 IEEE 1149.1 (JTAG) Boundary Scan
The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface
consists of four pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array, and
an instruction register. The JTAG pins are described in Table 2.5, “JTAG Pins,” on page 15. The JTAG
interface conforms to the IEEE Standard 1149.1 - 1990 Standard Test Access Port (TAP) and
Boundary-Scan Architecture.
All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI
are clocked into the test logic on the rising edge of TCK, while the output signal TDO is clocked on
the falling edge.
The JTAG logic is reset via a hardware reset or when the TMS and TDI pins are high for five TCK
periods.
The implemented IEEE 1149.1 instructions and their op codes are shown in Table 3.15.
Table 3.15 IEEE 1149.1 Op Codes
INSTRUCTION
Bypass
Sample/Preload
EXTEST
Clamp
HIGHZ
IDCODE
OP CODE
111
010
000
011
100
001
COMMENT
Mandatory Instruction
Mandatory Instruction
Mandatory Instruction
Optional Instruction
Optional Instruction
Optional Instruction
3.9.10
3.9.10.1
3.9.10.2
Note: All digital I/O pins support IEEE 1149.1 operation. Analog pins and the XO pin do not support
IEEE 1149.1 operation.
Advanced Features
The device implements several advanced features to enhance manageability of the Ethernet link.
These features are detailed in the following sub-sections.
Crossover Indicators
The device reports crossed channels in the XOVER Resolution 0:1 and XOVER Resolution 2:3 fields
of the User Status 2 Register. This feature is useful for trouble-shooting problems during network
installation.
Polarity Inversion Indicators
The device automatically detects and corrects inverted signal polarity. This is reported in the polarity
inversion bits (POLARITY_INV_3, POLARITY_INV_2, POLARITY_INV_1 and POLARITY_INV_0) of
the User Status 1 Register.
The polarity inversion bit for Channel 1 (POLARITY_INV_1) is valid after auto-negotiation is complete
as indicated by the Auto-Negotiate Complete bit of the Basic Status Register. The polarity inversion
bits for Channels 0, 2 and 3 (POLARITY_INV_0, POLARITY_INV_2, POLARITY_INV_3) are valid only
after the link is up as indicated by the Link Status bit of the Basic Status Register.
SMSC LAN8810/LAN8810i
39
DATASHEET
Revision 1.0 (02-06-13)