LAN8810I-AKZE Datasheet, PDF (44/100 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support

GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
4.2 Primary PHY Registers
The primary PHY registers are accessed via the SMI bus. An index is used to access individual primary
registers. Primary PHY register indexes are shown in Table 4.2, "PHY Control and Status Registers".
Additional read-only advanced registers are indirectly accessible via the Advanced Register Address
Port and Advanced Register Read Data Port. Section 4.3, "Advanced PHY Registers," on page 68
provides detailed information regarding the advanced registers.
Note: All unlisted register index values are not supported and should not be addressed.
Note: The NASR (Not Affected by Software Reset) designation is only applicable when the PHY Soft
Reset (RESET) bit of the Basic Control Register is set.
Table 4.2 PHY Control and Status Registers
INDEX
(IN DECIMAL)
0
1
2
3
4
5
6
7
8
9
10
15
16
17
18
19
20
21
27
29
30
31
REGISTER NAME
Basic Control Register
Basic Status Register
PHY Identifier 1 Register
PHY Identifier 2 Register
Auto Negotiation Advertisement Register
Auto Negotiation Link Partner Ability Register
Auto Negotiation Expansion Register
Auto Negotiation Next Page TX Register
Auto Negotiation Next Page RX Register
Master/Slave Control Register
Master/Slave Status Register
Extended Status Register
Link Control Register
10/100 Mode Control/Status Register
10/100 Special Modes Register
Extended Mode Control/Status Register
Advanced Register Address Port
Advanced Register Read Data Port
Control / Status Indications Register
Interrupt Source Flags Register
Interrupt Mask Register
PHY Special Control / Status Register
Revision 1.0 (02-06-13)
44
DATASHEET
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