LAN8810I-AKZE Datasheet, PDF (27/100 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support

GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
Note 3.3
To prevent an unexpected assertion of IRQ, the ENERGYON interrupt mask (INT7_EN)
should always be cleared as part of the ENERGYON interrupt service routine.
The transmitter FIFO depth can be adjusted via the Transmitter FIFO Depth field of the
Extended Mode Control/Status Register (19.10:9).
3.6
3.6.1
3.6.2
3.6.3
Resets
The device provides the following chip-level reset sources:
 Hardware Reset (nRESET)
 Software Reset
 Power-Down Reset
Hardware Reset (nRESET)
A hardware reset will occur when the system reset nRESET input pin is driven low. When nRESET is
asserted, it must be held low for the minimum time specified in Section 5.5.3, "Power-On Reset
Timing," on page 89 to ensure proper reset to the PHY. Following a hardware reset, the device resets
the device registers and relatches the configuration straps and CONFIG[3:0] pins.
Note: A hardware reset (nRESET assertion) is required following power-up. Refer to Section 5.5.3,
"Power-On Reset Timing," on page 89 for additional information.
Software Reset
A software reset is initiated by writing a ‘1’ to the PHY Soft Reset (RESET) bit of the Basic Control
Register. This self-clearing bit will return to ‘0’ after approximately 256μs, at which time the PHY reset
is complete. This reset initializes the logic within the PHY, with the exception of register bits marked
as “NASR” (Not Affected by Software Reset).
Following a software reset, the device configuration is reloaded from the register bit values, and not
from the configuration straps and CONFIG[3:0] pins. The device does not relatch the hardware
configuration settings. For example, if the device is powered up and a configuration strap is changed
from its initial power up state, a software reset will not load the new strap setting.
Power-Down Reset
A power-down reset is automatically activated when the device comes out of the power-down mode.
During power-down, the registers are not reset. Configuration straps and CONFIG[3:0] pins are not
latched as a result of a power-down reset. The power-down reset is internally extended by 256 μs after
exiting the power-down mode to allow the PLLs to stabilize before the logic is released from reset.
Refer to Section 3.7, "Power-Down modes," on page 28 for details on the various power-down modes.
SMSC LAN8810/LAN8810i
27
DATASHEET
Revision 1.0 (02-06-13)