LAN8810I-AKZE Datasheet, PDF (13/100 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support

GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
NUM
PINS
NAME
10BASE-T Link
LED Indicator
Reference
1
Clock Freq.
Select
Configuration
Strap
100BASE-TX
Link LED
Indicator
Hardware
Power Down
1
(HPD) Mode
Configuration
Strap
1000BASE-T
1
Link LED
Indicator
1
Link Activity
LED Indicator
Configuration
Input 0
1
Configuration
Input 1
1
Configuration
Input 2
1
Configuration
Input 3
1
Table 2.3 LED & Configuration Pins
SYMBOL
10_LED
REFCLK_SEL
100_LED
HPD_MODE
1000_LED
ACT_LED
CONFIG0
CONFIG1
CONFIG2
CONFIG3
BUFFER
TYPE
DESCRIPTION
VO8
VIS
(PD)
VO8
10BASE-T LED link indication. Refer to Section
3.9.1, "LEDs," on page 34 for additional
information.
This configuration strap is used to select the
reference clock frequency. When pulled-up, a
125MHz reference clock is selected. When pulled-
down, a 25MHz reference clock is selected.
See Note 2.2 for more information on configuration
straps.
100BASE-TX LED link indication. Refer to Section
3.9.1, "LEDs," on page 34 for additional
information.
VIS
(PD)
VO8
This configuration strap is used to select the
Hardware Power Down (HPD) mode. When pulled-
up, the PLL is not disabled when HPD is asserted.
When pulled-down, the PLL is disabled when HPD
is asserted.
Refer to Section 3.7.3, "Hardware Power-Down,"
on page 28 for additional information.
See Note 2.2 for more information on configuration
straps.
1000BASE-T LED link indication. Refer to Section
3.9.1, "LEDs," on page 34 for additional
information.
VO8
VIS
(PD)
VIS
(PD)
VIS
(PD)
VIS
(PD)
Link activity LED indication. Refer to Section 3.9.1,
"LEDs," on page 34 for additional information.
This pin sets the PHYADD[1:0] bits of the 10/100
Special Modes Register on reset or power-up. It
must be connected to VSS, 100_LED, 1000_LED,
or VDDVARIO. Refer to Section 3.8.1.2,
"CONFIG[3:0] Configuration Pins," on page 29 for
additional information.
This pin sets the PAUSE bit of the Auto Negotiation
Advertisement Register and PHYADD [2] bit of the
10/100 Special Modes Register on reset or power-
up. It must be connected to VSS, 100_LED,
1000_LED, or VDDVARIO. Refer to Section
3.8.1.2, "CONFIG[3:0] Configuration Pins," on
page 29 for additional information.
This pin sets the MOD[1:0] bits of the Extended
Mode Control/Status Register on reset or power-
up. It must be connected to VSS, 100_LED,
1000_LED, or VDDVARIO. Refer to Section
3.8.1.2, "CONFIG[3:0] Configuration Pins," on
page 29 for additional information.
This pin sets the CLK125DIS bit and MOD[3] bit of
the Extended Mode Control/Status Register on
reset or power-up. It must be connected to VSS,
100_LED, 1000_LED, or VDDVARIO. Refer to
Section 3.8.1.2, "CONFIG[3:0] Configuration Pins,"
on page 29 for additional information.
SMSC LAN8810/LAN8810i
13
DATASHEET
Revision 1.0 (02-06-13)