LAN8810I-AKZE Datasheet, PDF (40/100 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support

GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
3.9.10.3
3.9.10.4
3.9.10.5
3.9.10.6
3.9.10.7
Receive Error-Free Packets Counter
The quality of a link can be monitored by using the Receive Error-Free Packets Counter. The device
counts the number of good packets received and reports a 48-bit value across 3 advanced registers:
Receive Error-Free Packets Counter Low Register, Receive Error-Free Packets Counter Mid Register,
and Receive Error-Free Packets Counter High Register. The Receive Error-Free Packets Counter Low
Register latches the two other related counter registers and must always be read first. The Receive
Error-Free Packets Counter High Register register must be read last, and will automatically clear the
counter.
CRC Error Counter
This 48-bit counter counts the number of CRC errors detected. It’s value can be read across 3
advanced registers: CRC Error Counter Low Register, CRC Error Counter Mid Register, and CRC
Error Counter High Register. The CRC Error Counter Low Register latches the two other related
counter registers and must always be read first. The CRC Error Counter High Register must be read
last, and will automatically clear the counter.
Receive Error During Data Counter
This 16-bit counter counts the number of errors that occurred while data was being received. The value
is read from the Receive Error During Data Counter Register.
Receive Error During Idle Counter
This 16-bit counter counts the number of errors that occurred during idle. The value is read from the
Receive Error During Idle Counter Register register.
Transmitted Packets Counter
This 48-bit counter counts the number of packets that were transmitted. It’s value can be read across
3 advanced registers: Transmit Packet Counter Low Register, Transmit Packet Counter Mid Register,
and Transmit Packet Counter High Register. The Transmit Packet Counter Low Register latches the
two other related counter registers and must always be read first. The Transmit Packet Counter High
Register must be read last, and it will automatically clear the counter.
Revision 1.0 (02-06-13)
40
DATASHEET
SMSC LAN8810/LAN8810i