LAN8810I-AKZE Datasheet, PDF (31/100 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support

GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
Table 3.8 SMI Address Configuration with PAUSE=1
PHYADD[2:0]
000
001
010
011
100
101
110
111
CONFIG1
CPV(2)
CPV(2)
CPV(2)
CPV(2)
CPV(3)
CPV(3)
CPV(3)
CPV(3)
CONFIG0
CPV(0)
CPV(1)
CPV(2)
CPV(3)
CPV(0)
CPV(1)
CPV(2)
CPV(3)
3.8.1.2.2
CONFIGURING THE MODE OF OPERATION (CONFIG[3:2])
This section describes the initial modes of operation that are available using the CONFIG[3:2]
configuration pins. The user may configure additional modes using Software Configuration when the
CONFIG[3:2] options do not include the desired mode.
The CONFIG3 pin is used to configure the values of the MOD field (19.15:11) and the MACCLKDIS
bit (19.3) of the Extended Mode Control/Status Register. To select a default configuration mode via the
CONFIG[3:0] pins, the user must first select whether to enable or disable the MACCLK (MACCLKDIS
bit). The configuration pin values for CONFIG3 and CONFIG2 should be selected using Table 3.9 to
set MACCLKDIS=0, or Table 3.10 to set MACCLKDIS=1. These tables also detail how the MOD field
of the Extended Mode Control/Status Register will be configured.
Section 3.8.1.2.3 describes how the MOD field controls other configuration bits in the device. When a
soft reset is issued via the PHY Soft Reset (RESET) bit of the Basic Control Register, configuration is
controlled by the register bit values and the CONFIG[3:0] pins have no affect. Likewise, changing the
MOD field of the Extended Mode Control/Status Register bits does not change the configuration of the
device in this case.
Note: Table 3.9 and Table 3.10 utilize register index and bit number referencing in lieu of individual
names.
SMSC LAN8810/LAN8810i
31
DATASHEET
Revision 1.0 (02-06-13)