LAN8810I-AKZE Datasheet, PDF (57/100 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support

4.2.13 Link Control Register
Index (In Decimal): 16
GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
Size:
16 bits
BITS
DESCRIPTION
15:10
9:8
RESERVED
Speed Optimize Control
This register sets the number of Auto Negotiation attempts before the Speed
Optimize mechanism reduces the advertised speed.
00 = 7 attempts
01 = 5 attempts
10 = 4 attempts
11 = 3 attempts
Note: Refer to Section 3.9.7, "Speed Optimizer," on page 38 for additional
information.
7:6 RESERVED
5:4 Link Break Threshold
Idle error threshold for failing the link, if Link break in enabled.
00 = link break threshold is 10E-8.
01 = link break threshold is 10E-9.
10 = link break threshold is 10E-10.
11 = link break threshold is 10E-11
3
Link Break Enable
0 = link break is disabled
1 = link break is enabled
2
Power Optimization Disable
0 = Automatic power optimization is enabled
1 = Automatic power optimization is disabled (power consumption is
maximum)
1
RESERVED
0
LRST
Logic reset. This bit generates a reset that put all the logic into a known
state, but DOES NOT affect the register sets and 10/100 circuits. This bit is
NOT a self-clearing bit. Writing "1" to this bit generates synchronous reset.
TYPE
RO
R/W
RO
R/W
R/W
R/W
RO
RO
DEFAULT
-
00b
-
10b
0b
0b
-
-
SMSC LAN8810/LAN8810i
57
DATASHEET
Revision 1.0 (02-06-13)