LAN8810I-AKZE Datasheet, PDF (29/100 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support

GMII 10/100/1000 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
3.8 Configuration
The device mode of operation may be controlled by hardware and software (register-selectable)
configuration options. The initial configuration may be selected in hardware as described in
Section 3.8.1. In addition, register-selectable software configuration options may be used to further
define the functionality of the transceiver as described in Section 3.8.2. The device supports both IEEE
802.3-2005 compliant and vendor-specific register functions.
3.8.1 Hardware Configuration
Hardware configuration is controlled via multiple configuration straps and the CONFIG[3:0]
configuration pins. These items are detailed in the following sub-sections.
3.8.1.1
Configuration Straps
Configuration straps are multi-function pins that are driven as outputs during normal operation. During
a Hardware Reset (nRESET), these outputs are tri-stated. The high or low state of the signal is latched
following de-assertion of the reset and is used to determine the default configuration of a particular
feature. Table 3.5 details the configuration straps. Configuration straps are also listed as part of
Chapter 2, "Pin Description and Configuration," on page 10 with underlined names.
Configuration straps include internal resistors in order to prevent the signal from floating when
unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down
should be used to augment the internal resistor to ensure that it reaches the required voltage level
prior to latching. The internal resistor can also be overridden by the addition of an external resistor.
Note:
The system designer must guarantee that configuration straps meet the timing requirements
specified in Section 5.5.3, "Power-On Reset Timing," on page 89. If configuration straps are
not at the correct voltage level prior to being latched, the device may capture incorrect strap
values.
Note: Configuration straps must never be driven as inputs. If required, configuration straps can be
augmented, or overridden with external resistors.
Table 3.5 Configuration Straps
CONFIGURATION
STRAP
DESCRIPTION
MACCLK_SEL
REFCLK_SEL
HPD_MODE
Selects the MACCLK output clock frequency
Selects the reference clock frequency
Selects the hardware power-down (HPD) mode
LOGIC 0
(PD)
125MHz (Default)
25MHz (Default)
HPD with PLL
disabled (Default)
LOGIC 1
(PU)
25MHz
125MHz
HPD with PLL
enabled
3.8.1.2
CONFIG[3:0] Configuration Pins
The device provides 4 dedicated configuration pins, CONFIG[3:0], which are used to select the default
SMI address and mode of operation. The CONFIG[3:0] configuration pins differ from configuration
straps in that they are single-purpose pins and have different latch timing requirements. The high or
low states of the CONFIG[3:0] pins are latched following deassertion of a Hardware Reset (nRESET).
Refer to Section 5.5.3, "Power-On Reset Timing," on page 89 for additional CONFIG[3:0] timing
information.
Each CONFIG[3:0] configuration pin can be connected in one of four ways. The Configuration Pin
Value (CPV) represented by each connection option is shown in Table 3.6.
SMSC LAN8810/LAN8810i
29
DATASHEET
Revision 1.0 (02-06-13)