PIC16F610 Datasheet, PDF (69/180 Pages) Microchip Technology – 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F610/616/16HV610/616
REGISTER 8-4: SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0
SR1⁽²⁾
bit 7
R/W-0
SR0⁽²⁾
R/W-0
C1SEN
R/W-0
C2REN
R/S-0
PULSS
R/S-0
PULSR
U-0
R/W-0
—
SRCLKEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
S = Bit is set only -
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SR1: SR Latch Configuration bit⁽²⁾
1 = C2OUT pin is the latch Q output
0 = C2OUT pin is the C2 comparator output
bit 6
SR0: SR Latch Configuration bits⁽²⁾
1 = C1OUT pin is the latch Q output
0 = C1OUT pin is the C1 Comparator output
bit 5
C1SEN: C1 Set Enable bit
1 = C1 comparator output sets SR latch
0 = C1 comparator output has no effect on SR latch
bit 4
C2REN: C2 Reset Enable bit
1 = C2 comparator output resets SR latch
0 = C2 comparator output has no effect on SR latch
bit 3
PULSS: Pulse the SET Input of the SR Latch bit
1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 2
PULSR: Pulse the Reset Input of the SR Latch bit
1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 1
Unimplemented: Read as ‘0’
bit 0
SRCLKEN: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with SRCLK
0 = Set input of SR latch is not pulsed with the SRCLK
Note 1:
2:
The C1OUT and C2OUT bits in the CMxCON0 register will always reflect the actual comparator output (not the level on
the pin), regardless of the SR latch operation.
To enable an SR Latch output to the pin, the appropriate CxOE, and TRIS bits must be properly configured.
REGISTER 8-5: SRCON1: SR LATCH CONTROL 1 REGISTER
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
SRCS1
SRCS0
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
S = Bit is set only -
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-0
SRCS<1:0>: SR Latch Clock Prescale bits
00 = FOSC/16
01 = FOSC/32
10 = FOSC/64
11 = FOSC/128
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS41288C-page 67