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PIC16F610 Datasheet, PDF (46/180 Pages) Microchip Technology – 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers
PIC16F610/616/16HV610/616
5.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
5.1.3.1
Switching Prescaler Between
Timer0 and WDT Modules
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence
shown in Example 5-1 must be executed.
EXAMPLE 5-1:
CHANGING PRESCALER
(TIMER0 → WDT)
BANKSEL TMR0
;
CLRWDT
;Clear WDT
CLRF
TMR0
;Clear TMR0 and
;prescaler
BANKSEL OPTION_REG
;
BSF
OPTION_REG,PSA ;Select WDT
CLRWDT
;
;
MOVLW b’11111000’
;Mask prescaler
ANDWF OPTION_REG,W
;bits
IORLW b’00000101’
;Set WDT prescaler
MOVWF OPTION_REG
;to 1:32
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
EXAMPLE 5-2:
CHANGING PRESCALER
(WDT → TIMER0)
CLRWDT
;Clear WDT and
;prescaler
BANKSEL OPTION_REG ;
MOVLW b’11110000’ ;Mask TMR0 select and
ANDWF OPTION_REG,W ;prescaler bits
IORLW b’00000011’ ;Set prescale to 1:16
MOVWF OPTION_REG ;
5.1.4 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
5.1.5
USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
clock source must meet the timing requirements as
shown in Section 15.0 “Electrical Specifications”.
DS41288C-page 44
Preliminary
© 2007 Microchip Technology Inc.