PIC16F610 Datasheet, PDF (17/180 Pages) Microchip Technology – 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F610/616/16HV610/616
TABLE 2-2: PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 113
81h OPTION_REG RAPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 17, 113
82h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 22, 113
83h STATUS
IRP⁽¹⁾
RP1⁽¹⁾
RP0
TO
PD
Z
DC
C
0001 1xxx 16, 113
84h FSR
Indirect Data Memory Address Pointer
xxxx xxxx 22, 113
85h TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 31, 113
86h
—
Unimplemented
—
—
87h TRISC
—
—
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 40, 113
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah PCLATH
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 22, 113
8Bh INTCON
8Ch PIE1
GIE
PEIE
T0IE
INTE
RAIE
—
ADIE⁽³⁾ CCP1IE⁽³⁾ C2IE
C1IE
T0IF
—
INTF
RAIF 0000 0000 18, 113
TMR2IE⁽³⁾ TMR1IE -000 0-00 19, 113
8Dh
—
Unimplemented
—
—
8Eh PCON
—
—
—
—
—
—
POR
BOR ---- --qq 21, 113
8Fh
—
Unimplemented
—
—
90h OSCTUNE
91h ANSEL
92h PR2⁽³⁾
—
—
—
ANS7
ANS6
ANS5
Timer2 Module Period Register
TUN4
ANS4
TUN3
ANS3⁽³⁾
TUN2
ANS2⁽³⁾
TUN1
ANS1
TUN0
ANS0
---0 0000 29, 113
1111 1111 32, 114
1111 1111 53, 114
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h WPUA
—
—
WPUA5 WPUA4
—
WPUA2 WPUA1 WPUA0 --11 -111 33, 114
96h IOCA
—
—
IOCA5
IOCA4 IOCA3
IOCA2
IOCA1
IOCA0 --00 0000 33, 114
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h SRCON0
SR1
SR0
C1SEN C2REN PULSS PULSR
—
SRCLKEN 0000 00-0 67, 114
9Ah SRCON1
SRCS1 SRCS0
—
—
—
—
—
—
00-- ---- 67, 114
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
9Eh ADRESL⁽³⁾
9Fh ADCON1⁽³⁾
Unimplemented
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
—
ADCS2 ADCS1 ADCS0
—
—
—
—
—
xxxx xxxx 78, 114
—
-000 ---- 77, 114
Legend:
Note 1:
2:
3:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
PIC16F616/16HV616 only.
© 2007 Microchip Technology Inc.
Preliminary
DS41288C-page 15