PIC16F610 Datasheet, PDF (14/180 Pages) Microchip Technology – 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F610/616/16HV610/616
2.2 Data Memory Organization
The data memory (see Figure 2-4) is partitioned into
two banks, which contain the General Purpose
Registers (GPR) and the Special Function Registers
(SFR). The Special Function Registers are located in
the first 32 locations of each bank.
PIC16F610/16HV610 Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented
as static RAM. PIC16F616/16HV616 Register
locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1
are General Purpose Registers, implemented as static
RAM. Register locations F0h-FFh in Bank 1 point to
addresses 70h-7Fh in Bank 0. All other RAM is
unimplemented and returns ‘0’ when read. The RP0 bit
of the STATUS register is the bank select bit.
RP0
0 → Bank 0 is selected
1 → Bank 1 is selected
Note:
The IRP and RP1 bits of the STATUS
register are reserved and should always be
maintained as ‘0’s.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC16F610/16HV610 and 128 x 8 in the
PIC16F616/16HV616. Each register is accessed,
either directly or indirectly, through the File Select Reg-
ister (FSR) (see Section 2.4 “Indirect Addressing,
INDF and FSR Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
DS41288C-page 12
Preliminary
© 2007 Microchip Technology Inc.