PIC18F66K22-I Datasheet, PDF (542/550 Pages) Microchip Technology – PIC18F87K22 Family Data Sheet

PIC18F87K22 FAMILY
Power-Managed Modes ...................................................... 57
and EUSART Operation............................................ 331
and PWM Operation ................................................. 279
and SPI Operation .................................................... 289
Clock Transitions and Status Indicators...................... 58
Entering....................................................................... 57
Exiting Idle and Sleep Modes ..................................... 69
by Interrupt.......................................................... 69
by Reset.............................................................. 69
by WDT Time-out................................................ 69
Without an Oscillator Start-up Delay................... 69
Idle Modes .................................................................. 62
PRI_IDLE ............................................................ 63
RC_IDLE............................................................. 64
SEC_IDLE........................................................... 63
Multiple Sleep Commands .......................................... 58
Run Modes.................................................................. 58
PRI_RUN ............................................................ 58
RC_RUN ............................................................. 60
SEC_RUN........................................................... 58
Selecting ..................................................................... 57
Sleep Mode ................................................................. 62
OSC1 and OSC2 Pin States ............................... 55
Summary (table) ......................................................... 57
Power-on Reset (POR) ....................................................... 75
Power-up Delays................................................................. 55
Power-up Timer (PWRT)............................................... 55, 76
Time-out Sequence..................................................... 76
Prescaler, Timer0.............................................................. 195
Prescaler, Timer2.............................................................. 256
PRI_IDLE Mode .................................................................. 63
PRI_RUN Mode .................................................................. 58
Program Counter................................................................. 89
PCL, PCH and PCU Registers.................................... 89
PCLATH and PCLATU Registers ............................... 89
Program Memory
Code Protection ........................................................ 427
Extended Instruction Set ........................................... 107
Hard Memory Vectors ................................................. 88
Instructions.................................................................. 93
Two-Word ........................................................... 93
Interrupt Vector ........................................................... 88
Look-up Tables ........................................................... 91
Memory Maps ............................................................. 87
Reset Vector ............................................................... 88
Program Verification and Code Protection........................ 426
Associated Registers ................................................ 427
Programming, Device Instructions .................................... 431
PSP.See Parallel Slave Port.
Pulse Steering................................................................... 276
Pulse-Width Modulation. See PWM (CCP Module).
PUSH ................................................................................ 460
PUSH and POP Instructions ............................................... 90
PUSHL .............................................................................. 476
PWM (CCP Module)
Associated Registers ................................................ 256
Duty Cycle................................................................. 256
Example Frequencies/Resolutions ........................... 256
Period........................................................................ 255
Setup for PWM Operation ......................................... 256
TMR2 to PR2 Match ................................................. 255
PWM (ECCP Module)
Effects of a Reset ..................................................... 279
Operation in Power-Managed Modes ....................... 279
Operation with Fail-Safe Clock Monitor .................... 279
Pulse Steering Mode ................................................ 276
Steering Synchronization.......................................... 278
PWM Mode. See Enhanced Capture/Compare/PWM.
Q
Q Clock ............................................................................. 256
R
RAM. See Data Memory.
RC_IDLE Mode................................................................... 64
RC_RUN Mode................................................................... 60
RCALL .............................................................................. 461
RCON Register
Bit Status During Initialization ..................................... 78
Reader Response............................................................. 548
Real-Time Clock and Calendar (RTCC) ........................... 227
Registers .................................................................. 228
Reference Clock Output ..................................................... 53
Register File........................................................................ 96
Register File Summary ............................................... 98–103
Registers
ADCON0 (A/D Control 0).......................................... 352
ADCON1 (A/D Control 1).......................................... 353
ADCON2 (A/D Control 2).......................................... 354
ADRESH (A/D Result High Byte Left Justified,
ADFM = 0) ........................................................ 356
ADRESH (A/D Result High Byte Right Justified,
ADFM = 1) ....................................................... 357
ADRESL (A/D Result High Byte Left Justified,
ADFM = 0) ........................................................ 356
ADRESL (A/D Result Low Byte Right Justified,
ADFM = 1) ........................................................ 357
ALRMCFG (Alarm Configuration) ............................. 231
ALRMDAY (Alarm Day Value) .................................. 235
ALRMHR (Alarm Hours Value) ................................. 236
ALRMMIN (Alarm Minutes Value)............................. 236
ALRMMNTH (Alarm Month Value) ........................... 235
ALRMRPT (Alarm Repeat) ....................................... 232
ALRMSEC (Alarm Seconds Value) .......................... 236
ALRMWD (Alarm Weekday Value)........................... 235
ANCON0 (A/D Port Configuration 0) ........................ 358
ANCON1 (A/D Port Configuration 1) ........................ 358
ANCON2 (A/D Port Configuration 2) ........................ 359
BAUDCONx (Baud Rate Control) ............................. 330
CCPRxH (CCPx Period High Byte) .......................... 248
CCPRxL (CCPx Period Low Byte)............................ 248
CCPTMRS0 (CCP Timer Select 0)........................... 261
CCPTMRS1 (CCP Timer Select 1)........................... 246
CCPTMRS2 (CCP Timer Select 2)........................... 247
CCPxCON (CCP4-CCP10 Control) .......................... 245
CCPxCON (Enhanced Capture/Compare/
PWMx Control) ................................................. 260
CMSTAT (Comparator Status) ................................. 369
CMxCON (Comparator Control x)............................. 368
CONFIG1H (Configuration 1 High) ........................... 406
CONFIG1L (Configuration 1 Low) ............................ 405
CONFIG2H (Configuration 2 High) ........................... 408
CONFIG2L (Configuration 2 Low) ............................ 407
DS39960D-page 542
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