PIC18F66K22-I Datasheet, PDF (183/550 Pages) Microchip Technology – PIC18F87K22 Family Data Sheet

PIC18F87K22 FAMILY
12.8 PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISG and LATG.
PORTG is multiplexed with the AUSART and CCP,
ECCP, Analog, Comparator, RTCC and Timer input
functions (Table 12-13). When operating as I/O, all
PORTG pins have Schmitt Trigger input buffers. The
open-drain functionality for the CCPx and UART can be
configured using ODCONx.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS bit
settings. The pin override value is not loaded into the
TRIS register. This allows read-modify-write of the TRIS
register without concern due to peripheral overrides.
EXAMPLE 12-7: INITIALIZING PORTG
CLRF PORTG
; Initialize PORTG by
; clearing output
; data latches
BCF CM1CON, CON ; disable
; comparator 1
CLRF LATG
; Alternate method
; to clear output
; data latches
BANKSEL ANCON2
; Select bank with ACON2 register
MOVLW 0F0h
; make AN16 to AN19
; digital
MOVWF ANCON2
BANKSEL TRISG
; Select bank with TRISG register
MOVLW 04h
; Value used to
; initialize data
; direction
MOVWF TRISG
; Set RG1:RG0 as
; outputs
; RG2 as input
; RG4:RG3 as inputs
TABLE 12-13: PORTG FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/ECCP3/
P3A
RG0
0
O
DIG LATG<0> data output.
1
I
ST PORTG<0> data input.
ECCP3
0
O
DIG ECCP3 compare output and ECCP3 PWM output; takes priority over
port data.
1
I
ST ECCP3 capture input.
P3A
0
O
— ECCP3 PWM Output A.
May be configured for tri-state during Enhanced PWM shutdown
events.
RG1/TX2/CK2/
AN19/C3OUT
RG1
TX2
0
O
DIG LATG<1> data output.
1
I
ST PORTG<1> data input.
1
O
DIG Synchronous serial data output (EUSART module); takes priority over
port data.
CK2
1
O
DIG Synchronous serial data input (EUSART module); user must configure
as an input.
AN19
1
I
ST Synchronous serial clock input (EUSART module).
1
I
ANA A/D Input Channel 19.
Default input configuration on POR. Does not affect digital output.
Legend:
C3OUT
x
O
DIG Comparator 3 output.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
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DS39960D-page 183