PIC18F66K22-I Datasheet, PDF (36/550 Pages) Microchip Technology – PIC18F87K22 Family Data Sheet

PIC18F87K22 FAMILY
TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP ^{Type Type}
Description
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
I/O ST
Digital I/O.
O
—
External memory address latch enable.
RJ1/OE
RJ1
OE
61
I/O ST
Digital I/O.
O
—
External memory output enable.
RJ2/WRL
RJ2
WRL
60
I/O ST
Digital I/O.
O
—
External memory write low control.
RJ3/WRH
RJ3
WRH
59
I/O ST
Digital I/O.
O
—
External memory high control.
RJ4/BA0
RJ4
BA0
39
I/O ST
Digital I/O.
O
—
External Memory Byte Address 0 control
RJ5/CE
RJ5
CE
40
I/O ST
Digital I/O
O
—
External memory chip enable control.
RJ6/LB
RJ6
LB
41
I/O ST
Digital I/O.
O
—
External memory low byte control.
RJ7/UB
RJ7
UB
42
I/O ST
Digital I/O.
O
—
External memory high byte control.
VSS
11, 31, 51, 70 P
— Ground reference for logic and I/O pins.
VDD
32, 48, 71 P
— Positive supply for logic and I/O pins.
AVSS
26
P
— Ground reference for analog modules.
AVDD
25
P
— Positive supply for analog modules.
ENVREG
24
I
ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
12
Core logic power or external filter capacitor connection.
P
—
External filter capacitor connection (regulator
enabled/disabled).
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
P = Power
I²C = I²C™/SMBus
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
Note 1:
2:
3:
Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
Not available on PIC18F65K22 and PIC18F85K22 devices.
4: PSP is available only in Microcontroller mode.
5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).
DS39960D-page 36
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