PIC18F66K22-I Datasheet, PDF(171/550 Page) Microchip Technology – PIC18F87K22 Family Data Sheet

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PIC18F66K22-I Datasheet, PDF (171/550 Pages) Microchip Technology – PIC18F87K22 Family Data Sheet

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PIC18F87K22 FAMILY

TABLE 12-1: PORTA FUNCTIONS

Pin Name

Function

TRIS

Setting

I/O

I/O

Type

Description

RA0/AN0/ULPWU

RA0

AN0

0

O

DIG LATA<0> data output; not affected by analog input.

1

I

TTL PORTA<0> data input; disabled when analog input is enabled.

1

I

ANA A/D Input Channel 0. Default input configuration on POR; does not

affect digital output.

ULPWU

1

I

ANA Ultra Low-Power Wake-up input.

RA1/AN1

RA1

0

O

DIG LATA<1> data output; not affected by analog input.

1

I

TTL PORTA<1> data input; disabled when analog input is enabled.

AN1

1

I

ANA A/D Input Channel 1. Default input configuration on POR; does not

affect digital output.

RA2/AN2/VREF-

RA2

0

O

DIG LATA<2> data output; not affected by analog input.

1

I

TTL PORTA<2> data input; disabled when analog functions are enabled.

AN2

1

I

ANA A/D Input Channel 2. Default input configuration on POR.

VREF-

1

I

ANA A/D and comparator low reference voltage input.

RA3/AN3/VREF+

RA3

0

O

DIG LATA<3> data output; not affected by analog input.

1

I

TTL PORTA<3> data input; disabled when analog input is enabled.

AN3

1

I

ANA A/D Input Channel 3. Default input configuration on POR.

VREF+

1

I

ANA A/D and comparator high reference voltage input.

RA4/T0CKI

RA4

0

O

DIG LATA<4> data output.

1

I

ST PORTA<4> data input. Default configuration on POR.

T0CKI

x

I

ST Timer0 clock input.

RA5/AN4/T1CKI/

RA5

T3G/HLVDIN

0

O

DIG LATA<5> data output; not affected by analog input.

1

I

TTL PORTA<5> data input; disabled when analog input is enabled.

AN4

1

I

ANA A/D Input Channel 4. Default configuration on POR.

T1CKI

x

I

ST Timer1 clock input.

T3G

x

I

ST Timer3 external clock gate input.

HLVDIN

1

I

ANA High/Low-Voltage Detect (HLVD) external trip point input.

OSC2/CLKO/RA6

OSC2

CLKO

x

O ANA Main oscillator feedback output connection (HS, XT and LP modes).

x

O

DIG System cycle clock output (FOSC/4, EC and INTOSC modes).

RA6

0

O

DIG LATA<6> data output; disabled when FOSC2 Configuration bit is set.

1

I

TTL PORTA<6> data input; disabled when FOSC2 Configuration bit is set.

OSC1/CLKI/RA7

OSC1

x

I

ANA Main oscillator input connection (HS, XT and LP modes).

CLKI

x

I

ANA Main external clock source input (EC modes).

RA7

0

O

DIG LATA<7> data output; disabled when FOSC2 Configuration bit is set.

1

I

TTL PORTA<7> data input; disabled when FOSC2 Configuration bit is set.

Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,

TTL = TTL Buffer Input, x = Donât care (TRIS bit does not affect port direction or is overridden for this option).

TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTA

RA7(1)

RA6(1)

RA5

RA4

RA3

RA2

RA1

RA0

LATA

LATA7(1) LATA6(1)

LATA5

LATA4

LATA3

LATA2

LATA1

LATA0

TRISA

TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0

Legend: â = unimplemented, read as â0â. Shaded cells are not used by PORTA.

Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins,

they are disabled and read as âxâ.

ï£ 2009-2011 Microchip Technology Inc.

DS39960D-page 171

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