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PIC18F66K22-I Datasheet, PDF (177/550 Pages) Microchip Technology – PIC18F87K22 Family Data Sheet
PIC18F87K22 FAMILY
TABLE 12-7: PORTD FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RD3/PSP3/AD3
RD3
RD4/PSP4/
AD4/SDO2
RD5/PSP5/
AD5/SDI2/
SDA2
RD6/PSP6/
AD6/SCK2/
SCL2
PSP3(1)
AD3(2)
RD4
PSP4(1)
AD4(2)
SDO2
RD5
PSP5(1)
AD5(2)
SDI2
SDA2
RD6
PSP6(1)
AD6(2)
SCK2
SCL2
0
O
DIG LATD<3> data output.
1
I
ST PORTD<3> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 3.
0
O
DIG LATD<4> data output.
1
I
ST PORTD<4> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 4.
0
P
DOG SPI data output (MSSP module).
0
O
DIG LATD<5> data output.
1
I
ST PORTD<5> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 5.
1
I
ST SPI data input (MSSP module).
0
O
I2C I2C data input (MSSP module). Input type depends on module setting.
0
O
DIG LATD<6> data output.
1
I
ST PORTD<6> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 6.
0
O
DIG SPI clock output (MSSP module); takes priority over port data.
1
I
ST SPI clock input (MSSP module).
0
O
DIG I2C clock output (MSSP module); takes priority over port data.
1
I
I2C I2C clock input (MSSP module). Input type depends on module
setting.
RD7/PSP7/
AD7/SS2
RD7
PSP7(1)
AD7(2)
0
O
DIG LATD<7> data output.
1
I
ST PORTD<7> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 7.
Legend:
Note 1:
2:
SS2
1
I
TTL Slave select input for MSSP module.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
I2C = I2C™/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
The Parallel Slave Port (PSP) is available only in Microcontroller mode.
This feature is available only on PIC18F8XK22 devices.
TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
RD7
RD6
RD5
RD4
RD3
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
TRISD
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3
PADCFG1
RDPU
REPU
RJPU(1)
—
—
ODCON1 SSP1OD CCP2OD CCP1OD
—
—
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on PIC18F6XK22 devices, read as ‘0’.
RD2
LATD2
TRISD2
RTSECSEL1
—
RD1
LATD1
TRISD1
RESECSEL0
—
RD0
LATD0
TRISD0
—
SSP2OD
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DS39960D-page 177